dds.tan.qmsg

基于VHDL+FPGA的DDS信号发生设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|ram_block1a0~porta_address_reg0 memory rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[0\] 197.01 MHz 5.076 ns Internal " "Info: Clock \"clk\" has Internal fmax of 197.01 MHz between source memory \"rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[0\]\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X17_Y4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y4; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y4 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y4; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.906 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.906 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 236 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 236; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.708 ns) 2.906 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y4 1 " "Info: 2: + IC(0.729 ns) + CELL(0.708 ns) = 2.906 ns; Loc. = M4K_X17_Y4; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.437 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 74.91 % ) " "Info: Total cell delay = 2.177 ns ( 74.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.09 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.906 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.906 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.920 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 236 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 236; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.722 ns) 2.920 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X17_Y4 1 " "Info: 2: + IC(0.729 ns) + CELL(0.722 ns) = 2.920 ns; Loc. = M4K_X17_Y4; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.451 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 75.03 % ) " "Info: Total cell delay = 2.191 ns ( 75.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 24.97 % ) " "Info: Total interconnect delay = 0.729 ns ( 24.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.920 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.920 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.906 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.906 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.708ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.920 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.920 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.906 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.906 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.708ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.920 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.920 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "add_phase:u1\|phase\[13\] fctro\[1\] clk 6.868 ns register " "Info: tsu for register \"add_phase:u1\|phase\[13\]\" (data pin = \"fctro\[1\]\", clock pin = \"clk\") is 6.868 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.785 ns + Longest pin register " "Info: + Longest pin to register delay is 9.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fctro\[1\] 1 PIN PIN_161 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_161; Fanout = 3; PIN Node = 'fctro\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { fctro[1] } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.391 ns) + CELL(0.564 ns) 8.424 ns add_phase:u1\|phase\[1\]~94 2 COMB LC_X16_Y14_N3 2 " "Info: 2: + IC(6.391 ns) + CELL(0.564 ns) = 8.424 ns; Loc. = LC_X16_Y14_N3; Fanout = 2; COMB Node = 'add_phase:u1\|phase\[1\]~94'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.955 ns" { fctro[1] add_phase:u1|phase[1]~94 } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 8.602 ns add_phase:u1\|phase\[2\]~93 3 COMB LC_X16_Y14_N4 6 " "Info: 3: + IC(0.000 ns) + CELL(0.178 ns) = 8.602 ns; Loc. = LC_X16_Y14_N4; Fanout = 6; COMB Node = 'add_phase:u1\|phase\[2\]~93'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 8.810 ns add_phase:u1\|phase\[7\]~83 4 COMB LC_X16_Y14_N9 6 " "Info: 4: + IC(0.000 ns) + CELL(0.208 ns) = 8.810 ns; Loc. = LC_X16_Y14_N9; Fanout = 6; COMB Node = 'add_phase:u1\|phase\[7\]~83'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~83 } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 8.946 ns add_phase:u1\|phase\[12\]~88 5 COMB LC_X16_Y13_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.136 ns) = 8.946 ns; Loc. = LC_X16_Y13_N4; Fanout = 3; COMB Node = 'add_phase:u1\|phase\[12\]~88'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { add_phase:u1|phase[7]~83 add_phase:u1|phase[12]~88 } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 9.785 ns add_phase:u1\|phase\[13\] 6 REG LC_X16_Y13_N5 4 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 9.785 ns; Loc. = LC_X16_Y13_N5; Fanout = 4; REG Node = 'add_phase:u1\|phase\[13\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { add_phase:u1|phase[12]~88 add_phase:u1|phase[13] } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.394 ns ( 34.69 % ) " "Info: Total cell delay = 3.394 ns ( 34.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.391 ns ( 65.31 % ) " "Info: Total interconnect delay = 6.391 ns ( 65.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.785 ns" { fctro[1] add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~83 add_phase:u1|phase[12]~88 add_phase:u1|phase[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.785 ns" { fctro[1] fctro[1]~out0 add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~83 add_phase:u1|phase[12]~88 add_phase:u1|phase[13] } { 0.000ns 0.000ns 6.391ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.564ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 236 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 236; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns add_phase:u1\|phase\[13\] 2 REG LC_X16_Y13_N5 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X16_Y13_N5; Fanout = 4; REG Node = 'add_phase:u1\|phase\[13\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk add_phase:u1|phase[13] } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk add_phase:u1|phase[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 add_phase:u1|phase[13] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.785 ns" { fctro[1] add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~83 add_phase:u1|phase[12]~88 add_phase:u1|phase[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.785 ns" { fctro[1] fctro[1]~out0 add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~83 add_phase:u1|phase[12]~88 add_phase:u1|phase[13] } { 0.000ns 0.000ns 6.391ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.564ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk add_phase:u1|phase[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 add_phase:u1|phase[13] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk addout\[6\] rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[6\] 8.867 ns memory " "Info: tco from clock \"clk\" to destination pin \"addout\[6\]\" through memory \"rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[6\]\" is 8.867 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.939 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 236 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 236; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.708 ns) 2.939 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[6\] 2 MEM M4K_X17_Y12 1 " "Info: 2: + IC(0.762 ns) + CELL(0.708 ns) = 2.939 ns; Loc. = M4K_X17_Y12; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.470 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 74.07 % ) " "Info: Total cell delay = 2.177 ns ( 74.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.93 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.939 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.939 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.278 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[6\] 1 MEM M4K_X17_Y12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X17_Y12; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\|q_a\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.050 ns) + CELL(2.124 ns) 5.278 ns addout\[6\] 2 PIN PIN_159 0 " "Info: 2: + IC(3.050 ns) + CELL(2.124 ns) = 5.278 ns; Loc. = PIN_159; Fanout = 0; PIN Node = 'addout\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.174 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] addout[6] } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.228 ns ( 42.21 % ) " "Info: Total cell delay = 2.228 ns ( 42.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.050 ns ( 57.79 % ) " "Info: Total interconnect delay = 3.050 ns ( 57.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.278 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] addout[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.278 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] addout[6] } { 0.000ns 3.050ns } { 0.104ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.939 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.939 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.708ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.278 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] addout[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.278 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6] addout[6] } { 0.000ns 3.050ns } { 0.104ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "add_phase:u1\|phase\[15\] fctro\[15\] clk -0.837 ns register " "Info: th for register \"add_phase:u1\|phase\[15\]\" (data pin = \"fctro\[15\]\", clock pin = \"clk\") is -0.837 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 236 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 236; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns add_phase:u1\|phase\[15\] 2 REG LC_X16_Y13_N7 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X16_Y13_N7; Fanout = 2; REG Node = 'add_phase:u1\|phase\[15\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk add_phase:u1|phase[15] } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk add_phase:u1|phase[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 add_phase:u1|phase[15] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.806 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.806 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fctro\[15\] 1 PIN PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'fctro\[15\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { fctro[15] } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.028 ns) + CELL(0.309 ns) 3.806 ns add_phase:u1\|phase\[15\] 2 REG LC_X16_Y13_N7 2 " "Info: 2: + IC(2.028 ns) + CELL(0.309 ns) = 3.806 ns; Loc. = LC_X16_Y13_N7; Fanout = 2; REG Node = 'add_phase:u1\|phase\[15\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.337 ns" { fctro[15] add_phase:u1|phase[15] } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 46.72 % ) " "Info: Total cell delay = 1.778 ns ( 46.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.028 ns ( 53.28 % ) " "Info: Total interconnect delay = 2.028 ns ( 53.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.806 ns" { fctro[15] add_phase:u1|phase[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.806 ns" { fctro[15] fctro[15]~out0 add_phase:u1|phase[15] } { 0.000ns 0.000ns 2.028ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk add_phase:u1|phase[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 add_phase:u1|phase[15] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.806 ns" { fctro[15] add_phase:u1|phase[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.806 ns" { fctro[15] fctro[15]~out0 add_phase:u1|phase[15] } { 0.000ns 0.000ns 2.028ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}