prev_cmp_dds.tan.qmsg

基于VHDL+FPGA的DDS信号发生设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|ram_block1a0~porta_address_reg0 memory rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[0\] 197.01 MHz 5.076 ns Internal " "Info: Clock \"clk\" has Internal fmax of 197.01 MHz between source memory \"rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[0\]\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X17_Y13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y13; Fanout = 4; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_4741.tdf" "" { Text "F:/desige/dds/db/altsyncram_4741.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y13 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y13; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_4741.tdf" "" { Text "F:/desige/dds/db/altsyncram_4741.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.959 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.708 ns) 2.959 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y13 1 " "Info: 2: + IC(0.782 ns) + CELL(0.708 ns) = 2.959 ns; Loc. = M4K_X17_Y13; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_4741.tdf" "" { Text "F:/desige/dds/db/altsyncram_4741.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 73.57 % ) " "Info: Total cell delay = 2.177 ns ( 73.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.43 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.973 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.722 ns) 2.973 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X17_Y13 4 " "Info: 2: + IC(0.782 ns) + CELL(0.722 ns) = 2.973 ns; Loc. = M4K_X17_Y13; Fanout = 4; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_4741.tdf" "" { Text "F:/desige/dds/db/altsyncram_4741.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 73.70 % ) " "Info: Total cell delay = 2.191 ns ( 73.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.30 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.708ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_4741.tdf" "" { Text "F:/desige/dds/db/altsyncram_4741.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_4741.tdf" "" { Text "F:/desige/dds/db/altsyncram_4741.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.708ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "add_phase:u1\|phase\[13\] fctro\[1\] clk 7.262 ns register " "Info: tsu for register \"add_phase:u1\|phase\[13\]\" (data pin = \"fctro\[1\]\", clock pin = \"clk\") is 7.262 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.187 ns + Longest pin register " "Info: + Longest pin to register delay is 10.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns fctro\[1\] 1 PIN PIN_88 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_88; Fanout = 3; PIN Node = 'fctro\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { fctro[1] } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.787 ns) + CELL(0.564 ns) 8.826 ns add_phase:u1\|phase\[1\]~94 2 COMB LC_X19_Y14_N3 2 " "Info: 2: + IC(6.787 ns) + CELL(0.564 ns) = 8.826 ns; Loc. = LC_X19_Y14_N3; Fanout = 2; COMB Node = 'add_phase:u1\|phase\[1\]~94'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.351 ns" { fctro[1] add_phase:u1|phase[1]~94 } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 9.004 ns add_phase:u1\|phase\[2\]~93 3 COMB LC_X19_Y14_N4 6 " "Info: 3: + IC(0.000 ns) + CELL(0.178 ns) = 9.004 ns; Loc. = LC_X19_Y14_N4; Fanout = 6; COMB Node = 'add_phase:u1\|phase\[2\]~93'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 9.212 ns add_phase:u1\|phase\[7\]~81 4 COMB LC_X19_Y14_N9 6 " "Info: 4: + IC(0.000 ns) + CELL(0.208 ns) = 9.212 ns; Loc. = LC_X19_Y14_N9; Fanout = 6; COMB Node = 'add_phase:u1\|phase\[7\]~81'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~81 } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 9.348 ns add_phase:u1\|phase\[12\]~86 5 COMB LC_X19_Y13_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.136 ns) = 9.348 ns; Loc. = LC_X19_Y13_N4; Fanout = 3; COMB Node = 'add_phase:u1\|phase\[12\]~86'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { add_phase:u1|phase[7]~81 add_phase:u1|phase[12]~86 } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 10.187 ns add_phase:u1\|phase\[13\] 6 REG LC_X19_Y13_N5 4 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 10.187 ns; Loc. = LC_X19_Y13_N5; Fanout = 4; REG Node = 'add_phase:u1\|phase\[13\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { add_phase:u1|phase[12]~86 add_phase:u1|phase[13] } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 33.38 % ) " "Info: Total cell delay = 3.400 ns ( 33.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.787 ns ( 66.62 % ) " "Info: Total interconnect delay = 6.787 ns ( 66.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.187 ns" { fctro[1] add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~81 add_phase:u1|phase[12]~86 add_phase:u1|phase[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.187 ns" { fctro[1] fctro[1]~out0 add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~81 add_phase:u1|phase[12]~86 add_phase:u1|phase[13] } { 0.000ns 0.000ns 6.787ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.564ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns add_phase:u1\|phase\[13\] 2 REG LC_X19_Y13_N5 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X19_Y13_N5; Fanout = 4; REG Node = 'add_phase:u1\|phase\[13\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk add_phase:u1|phase[13] } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk add_phase:u1|phase[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 add_phase:u1|phase[13] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.187 ns" { fctro[1] add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~81 add_phase:u1|phase[12]~86 add_phase:u1|phase[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.187 ns" { fctro[1] fctro[1]~out0 add_phase:u1|phase[1]~94 add_phase:u1|phase[2]~93 add_phase:u1|phase[7]~81 add_phase:u1|phase[12]~86 add_phase:u1|phase[13] } { 0.000ns 0.000ns 6.787ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.564ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk add_phase:u1|phase[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 add_phase:u1|phase[13] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk addout\[3\] rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[3\] 9.458 ns memory " "Info: tco from clock \"clk\" to destination pin \"addout\[3\]\" through memory \"rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[3\]\" is 9.458 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.959 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.708 ns) 2.959 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[3\] 2 MEM M4K_X17_Y13 1 " "Info: 2: + IC(0.782 ns) + CELL(0.708 ns) = 2.959 ns; Loc. = M4K_X17_Y13; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_4741.tdf" "" { Text "F:/desige/dds/db/altsyncram_4741.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 73.57 % ) " "Info: Total cell delay = 2.177 ns ( 73.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.43 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_4741.tdf" "" { Text "F:/desige/dds/db/altsyncram_4741.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.849 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[3\] 1 MEM M4K_X17_Y13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X17_Y13; Fanout = 1; MEM Node = 'rom:u2\|altsyncram:altsyncram_component\|altsyncram_4741:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_4741.tdf" "" { Text "F:/desige/dds/db/altsyncram_4741.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.637 ns) + CELL(2.108 ns) 5.849 ns addout\[3\] 2 PIN PIN_105 0 " "Info: 2: + IC(3.637 ns) + CELL(2.108 ns) = 5.849 ns; Loc. = PIN_105; Fanout = 0; PIN Node = 'addout\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.745 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] addout[3] } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns ( 37.82 % ) " "Info: Total cell delay = 2.212 ns ( 37.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.637 ns ( 62.18 % ) " "Info: Total interconnect delay = 3.637 ns ( 62.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.849 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] addout[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.849 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] addout[3] } { 0.000ns 3.637ns } { 0.104ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { clk rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { clk clk~out0 rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.708ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.849 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] addout[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.849 ns" { rom:u2|altsyncram:altsyncram_component|altsyncram_4741:auto_generated|q_a[3] addout[3] } { 0.000ns 3.637ns } { 0.104ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "add_phase:u1\|phase\[7\] fctro\[7\] clk -4.987 ns register " "Info: th for register \"add_phase:u1\|phase\[7\]\" (data pin = \"fctro\[7\]\", clock pin = \"clk\") is -4.987 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns add_phase:u1\|phase\[7\] 2 REG LC_X19_Y14_N9 3 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X19_Y14_N9; Fanout = 3; REG Node = 'add_phase:u1\|phase\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk add_phase:u1|phase[7] } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk add_phase:u1|phase[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 add_phase:u1|phase[7] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.964 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.964 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns fctro\[7\] 1 PIN PIN_214 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_214; Fanout = 2; PIN Node = 'fctro\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { fctro[7] } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.882 ns) + CELL(0.607 ns) 7.964 ns add_phase:u1\|phase\[7\] 2 REG LC_X19_Y14_N9 3 " "Info: 2: + IC(5.882 ns) + CELL(0.607 ns) = 7.964 ns; Loc. = LC_X19_Y14_N9; Fanout = 3; REG Node = 'add_phase:u1\|phase\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.489 ns" { fctro[7] add_phase:u1|phase[7] } "NODE_NAME" } } { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 26.14 % ) " "Info: Total cell delay = 2.082 ns ( 26.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.882 ns ( 73.86 % ) " "Info: Total interconnect delay = 5.882 ns ( 73.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.964 ns" { fctro[7] add_phase:u1|phase[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.964 ns" { fctro[7] fctro[7]~out0 add_phase:u1|phase[7] } { 0.000ns 0.000ns 5.882ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk add_phase:u1|phase[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 add_phase:u1|phase[7] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.964 ns" { fctro[7] add_phase:u1|phase[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.964 ns" { fctro[7] fctro[7]~out0 add_phase:u1|phase[7] } { 0.000ns 0.000ns 5.882ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}