add_phase.vhd.bak

基于VHDL+FPGA的DDS信号发生设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add_phase is 
port(
clk:in std_logic;
fc:in std_logic_vector(15 downto 0);
adderss:out std_logic_vector(15 downto 0)
);end add_phase;
architecture add_phase of add_phase is
signal phase: std_logic_vector (15 downto 0);
 begin
 process(clk)
begin
    if clk'event and clk='1'then
if phase<="1111111111111111"then
   phase<=phase+fc; 
else 
 phase<="0000000000000000";
end if;
adderss<=phase;--out 16 bit adderss 
end if;
end process;
end add_phase;