dds.map.summary

基于VHDL+FPGA的DDS信号发生设计

Analysis & Synthesis Status : Successful - Wed Oct 01 16:34:10 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : dds
Top-level Entity Name : dds
Family : Cyclone
Total logic elements : 28
Total pins : 33
Total virtual pins : 0
Total memory bits : 65,536
Total PLLs : 0