dds.sim.rpt

基于VHDL+FPGA的DDS信号发生设计

; |dds|addout[10]                                                                          ; |dds|addout[10]                                                                    ; padio            ;
; |dds|addout[11]                                                                          ; |dds|addout[11]                                                                    ; padio            ;
; |dds|addout[12]                                                                          ; |dds|addout[12]                                                                    ; padio            ;
; |dds|addout[13]                                                                          ; |dds|addout[13]                                                                    ; padio            ;
; |dds|addout[14]                                                                          ; |dds|addout[14]                                                                    ; padio            ;
; |dds|addout[15]                                                                          ; |dds|addout[15]                                                                    ; padio            ;
; |dds|clk                                                                                 ; |dds|clk~corein                                                                    ; combout          ;
+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                               ;
+-------------------------------+-------------------------------------+------------------+
; Node Name                     ; Output Port Name                    ; Output Port Type ;
+-------------------------------+-------------------------------------+------------------+
; |dds|add_phase:u1|phase[4]    ; |dds|add_phase:u1|phase[4]~80       ; cout0            ;
; |dds|add_phase:u1|phase[4]    ; |dds|add_phase:u1|phase[4]~80COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[5]    ; |dds|add_phase:u1|phase[5]~81       ; cout0            ;
; |dds|add_phase:u1|phase[5]    ; |dds|add_phase:u1|phase[5]~81COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[6]    ; |dds|add_phase:u1|phase[6]~82       ; cout0            ;
; |dds|add_phase:u1|phase[6]    ; |dds|add_phase:u1|phase[6]~82COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[7]    ; |dds|add_phase:u1|phase[7]~83       ; cout             ;
; |dds|add_phase:u1|phase[8]    ; |dds|add_phase:u1|phase[8]~84       ; cout0            ;
; |dds|add_phase:u1|phase[8]    ; |dds|add_phase:u1|phase[8]~84COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[9]    ; |dds|add_phase:u1|phase[9]~85       ; cout0            ;
; |dds|add_phase:u1|phase[9]    ; |dds|add_phase:u1|phase[9]~85COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[10]   ; |dds|add_phase:u1|phase[10]~86      ; cout0            ;
; |dds|add_phase:u1|phase[10]   ; |dds|add_phase:u1|phase[10]~86COUT1 ; cout1            ;
; |dds|add_phase:u1|phase[11]   ; |dds|add_phase:u1|phase[11]~87      ; cout0            ;
; |dds|add_phase:u1|phase[11]   ; |dds|add_phase:u1|phase[11]~87COUT1 ; cout1            ;
; |dds|add_phase:u1|phase[13]   ; |dds|add_phase:u1|phase[13]~89COUT1 ; cout1            ;
; |dds|add_phase:u1|phase[14]   ; |dds|add_phase:u1|phase[14]~90COUT1 ; cout1            ;
; |dds|add_phase:u1|phase[3]    ; |dds|add_phase:u1|phase[3]~92       ; cout0            ;
; |dds|add_phase:u1|phase[3]    ; |dds|add_phase:u1|phase[3]~92COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[2]    ; |dds|add_phase:u1|phase[2]~93       ; cout             ;
; |dds|add_phase:u1|phase[1]    ; |dds|add_phase:u1|phase[1]~94       ; cout0            ;
; |dds|add_phase:u1|phase[1]    ; |dds|add_phase:u1|phase[1]~94COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[0]    ; |dds|add_phase:u1|phase[0]~95       ; cout0            ;
; |dds|add_phase:u1|phase[0]    ; |dds|add_phase:u1|phase[0]~95COUT1  ; cout1            ;
; |dds|add_phase:u1|adderss[4]  ; |dds|add_phase:u1|adderss[4]        ; regout           ;
; |dds|add_phase:u1|adderss[5]  ; |dds|add_phase:u1|adderss[5]        ; regout           ;
; |dds|add_phase:u1|adderss[6]  ; |dds|add_phase:u1|adderss[6]        ; regout           ;
; |dds|add_phase:u1|adderss[7]  ; |dds|add_phase:u1|adderss[7]        ; regout           ;
; |dds|add_phase:u1|adderss[8]  ; |dds|add_phase:u1|adderss[8]        ; regout           ;
; |dds|add_phase:u1|adderss[9]  ; |dds|add_phase:u1|adderss[9]        ; regout           ;
; |dds|add_phase:u1|adderss[10] ; |dds|add_phase:u1|adderss[10]       ; regout           ;
; |dds|add_phase:u1|adderss[11] ; |dds|add_phase:u1|adderss[11]       ; regout           ;
; |dds|fctro[4]                 ; |dds|fctro[4]~corein                ; combout          ;
; |dds|fctro[5]                 ; |dds|fctro[5]~corein                ; combout          ;
; |dds|fctro[6]                 ; |dds|fctro[6]~corein                ; combout          ;
; |dds|fctro[7]                 ; |dds|fctro[7]~corein                ; combout          ;
; |dds|fctro[8]                 ; |dds|fctro[8]~corein                ; combout          ;
; |dds|fctro[9]                 ; |dds|fctro[9]~corein                ; combout          ;
; |dds|fctro[10]                ; |dds|fctro[10]~corein               ; combout          ;
; |dds|fctro[11]                ; |dds|fctro[11]~corein               ; combout          ;
; |dds|fctro[12]                ; |dds|fctro[12]~corein               ; combout          ;
; |dds|fctro[13]                ; |dds|fctro[13]~corein               ; combout          ;
; |dds|fctro[14]                ; |dds|fctro[14]~corein               ; combout          ;
; |dds|fctro[15]                ; |dds|fctro[15]~corein               ; combout          ;
; |dds|fctro[3]                 ; |dds|fctro[3]~corein                ; combout          ;
; |dds|fctro[2]                 ; |dds|fctro[2]~corein                ; combout          ;
; |dds|fctro[1]                 ; |dds|fctro[1]~corein                ; combout          ;
; |dds|fctro[0]                 ; |dds|fctro[0]~corein                ; combout          ;
+-------------------------------+-------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                               ;
+-------------------------------+-------------------------------------+------------------+
; Node Name                     ; Output Port Name                    ; Output Port Type ;
+-------------------------------+-------------------------------------+------------------+
; |dds|add_phase:u1|phase[4]    ; |dds|add_phase:u1|phase[4]~80       ; cout0            ;
; |dds|add_phase:u1|phase[4]    ; |dds|add_phase:u1|phase[4]~80COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[5]    ; |dds|add_phase:u1|phase[5]~81       ; cout0            ;
; |dds|add_phase:u1|phase[5]    ; |dds|add_phase:u1|phase[5]~81COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[6]    ; |dds|add_phase:u1|phase[6]~82       ; cout0            ;
; |dds|add_phase:u1|phase[6]    ; |dds|add_phase:u1|phase[6]~82COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[7]    ; |dds|add_phase:u1|phase[7]~83       ; cout             ;
; |dds|add_phase:u1|phase[8]    ; |dds|add_phase:u1|phase[8]~84       ; cout0            ;
; |dds|add_phase:u1|phase[8]    ; |dds|add_phase:u1|phase[8]~84COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[9]    ; |dds|add_phase:u1|phase[9]~85       ; cout0            ;
; |dds|add_phase:u1|phase[9]    ; |dds|add_phase:u1|phase[9]~85COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[10]   ; |dds|add_phase:u1|phase[10]~86      ; cout0            ;
; |dds|add_phase:u1|phase[10]   ; |dds|add_phase:u1|phase[10]~86COUT1 ; cout1            ;
; |dds|add_phase:u1|phase[11]   ; |dds|add_phase:u1|phase[11]~87      ; cout0            ;
; |dds|add_phase:u1|phase[11]   ; |dds|add_phase:u1|phase[11]~87COUT1 ; cout1            ;
; |dds|add_phase:u1|phase[13]   ; |dds|add_phase:u1|phase[13]~89COUT1 ; cout1            ;
; |dds|add_phase:u1|phase[14]   ; |dds|add_phase:u1|phase[14]~90COUT1 ; cout1            ;
; |dds|add_phase:u1|phase[3]    ; |dds|add_phase:u1|phase[3]~92       ; cout0            ;
; |dds|add_phase:u1|phase[3]    ; |dds|add_phase:u1|phase[3]~92COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[2]    ; |dds|add_phase:u1|phase[2]~93       ; cout             ;
; |dds|add_phase:u1|phase[1]    ; |dds|add_phase:u1|phase[1]~94       ; cout0            ;
; |dds|add_phase:u1|phase[1]    ; |dds|add_phase:u1|phase[1]~94COUT1  ; cout1            ;
; |dds|add_phase:u1|phase[0]    ; |dds|add_phase:u1|phase[0]~95       ; cout0            ;
; |dds|add_phase:u1|phase[0]    ; |dds|add_phase:u1|phase[0]~95COUT1  ; cout1            ;
; |dds|add_phase:u1|adderss[4]  ; |dds|add_phase:u1|adderss[4]        ; regout           ;
; |dds|add_phase:u1|adderss[5]  ; |dds|add_phase:u1|adderss[5]        ; regout           ;
; |dds|add_phase:u1|adderss[6]  ; |dds|add_phase:u1|adderss[6]        ; regout           ;
; |dds|add_phase:u1|adderss[7]  ; |dds|add_phase:u1|adderss[7]        ; regout           ;
; |dds|add_phase:u1|adderss[8]  ; |dds|add_phase:u1|adderss[8]        ; regout           ;
; |dds|add_phase:u1|adderss[9]  ; |dds|add_phase:u1|adderss[9]        ; regout           ;
; |dds|add_phase:u1|adderss[10] ; |dds|add_phase:u1|adderss[10]       ; regout           ;
; |dds|add_phase:u1|adderss[11] ; |dds|add_phase:u1|adderss[11]       ; regout           ;
; |dds|fctro[4]                 ; |dds|fctro[4]~corein                ; combout          ;
; |dds|fctro[5]                 ; |dds|fctro[5]~corein                ; combout          ;
; |dds|fctro[6]                 ; |dds|fctro[6]~corein                ; combout          ;
; |dds|fctro[7]                 ; |dds|fctro[7]~corein                ; combout          ;
; |dds|fctro[8]                 ; |dds|fctro[8]~corein                ; combout          ;
; |dds|fctro[9]                 ; |dds|fctro[9]~corein                ; combout          ;
; |dds|fctro[10]                ; |dds|fctro[10]~corein               ; combout          ;
; |dds|fctro[11]                ; |dds|fctro[11]~corein               ; combout          ;
; |dds|fctro[12]                ; |dds|fctro[12]~corein               ; combout          ;
; |dds|fctro[13]                ; |dds|fctro[13]~corein               ; combout          ;
; |dds|fctro[14]                ; |dds|fctro[14]~corein               ; combout          ;
; |dds|fctro[15]                ; |dds|fctro[15]~corein               ; combout          ;
; |dds|fctro[3]                 ; |dds|fctro[3]~corein                ; combout          ;
; |dds|fctro[2]                 ; |dds|fctro[2]~corein                ; combout          ;
; |dds|fctro[1]                 ; |dds|fctro[1]~corein                ; combout          ;
; |dds|fctro[0]                 ; |dds|fctro[0]~corein                ; combout          ;
+-------------------------------+-------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Oct 01 16:55:27 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off dds -c dds
Info: Using vector source file "F:/desige/dds/dds.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      45.45 %
Info: Number of transitions in simulation is 2514
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Wed Oct 01 16:55:29 2008
    Info: Elapsed time: 00:00:02