dds.tan.summary

基于VHDL+FPGA的DDS信号发生设计

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.868 ns
From           : fctro[1]
To             : add_phase:u1|phase[15]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.867 ns
From           : rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[6]
To             : addout[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.837 ns
From           : fctro[15]
To             : add_phase:u1|phase[15]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ram_block1a15~porta_address_reg11
To             : rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|q_a[15]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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