dds.fit.summary

基于VHDL+FPGA的DDS信号发生设计

Fitter Status : Successful - Wed Oct 01 16:34:17 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : dds
Top-level Entity Name : dds
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 28 / 5,980 ( < 1 % )
Total pins : 33 / 185 ( 18 % )
Total virtual pins : 0
Total memory bits : 65,536 / 92,160 ( 71 % )
Total PLLs : 0 / 2 ( 0 % )