📄 dds.map.rpt
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; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 28 ;
; Total logic cells in carry chains ; 16 ;
; I/O pins ; 33 ;
; Total memory bits ; 65536 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 44 ;
; Total fan-out ; 311 ;
; Average fan-out ; 4.04 ;
+---------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------+--------------+
; |dds ; 28 (0) ; 28 ; 65536 ; 33 ; 0 ; 0 (0) ; 12 (0) ; 16 (0) ; 16 (0) ; 0 (0) ; |dds ; work ;
; |add_phase:u1| ; 28 (28) ; 28 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (12) ; 16 (16) ; 16 (16) ; 0 (0) ; |dds|add_phase:u1 ; work ;
; |rom:u2| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |dds|rom:u2 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |dds|rom:u2|altsyncram:altsyncram_component ; work ;
; |altsyncram_5i31:auto_generated| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |dds|rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated ; work ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+----------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+----------------+
; rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 4096 ; 16 ; -- ; -- ; 65536 ; d:\romdata.mif ;
+----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+----------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 28 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------------+
; Source assignments for rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------+
+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom:u2|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+-------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+-------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 16 ; Signed Integer ;
; WIDTHAD_A ; 12 ; Signed Integer ;
; NUMWORDS_A ; 4096 ; Signed Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; d:\romdata.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_5i31 ; Untyped ;
+------------------------------------+----------------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Wed Oct 01 16:34:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds
Info: Found 3 design units, including 1 entities, in source file dds.vhd
Info: Found design unit 1: my_copponent
Info: Found design unit 2: dds-dds
Info: Found entity 1: dds
Info: Found 2 design units, including 1 entities, in source file add_phase.vhd
Info: Found design unit 1: add_phase-add_phase
Info: Found entity 1: add_phase
Info: Elaborating entity "dds" for the top level hierarchy
Info: Elaborating entity "add_phase" for hierarchy "add_phase:u1"
Warning: Using design file rom.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: rom-SYN
Info: Found entity 1: rom
Info: Elaborating entity "rom" for hierarchy "rom:u2"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "rom:u2|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "rom:u2|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5i31.tdf
Info: Found entity 1: altsyncram_5i31
Info: Elaborating entity "altsyncram_5i31" for hierarchy "rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated"
Info: Implemented 77 device resources after synthesis - the final resource count might be different
Info: Implemented 17 input pins
Info: Implemented 16 output pins
Info: Implemented 28 logic cells
Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 151 megabytes of memory during processing
Info: Processing ended: Wed Oct 01 16:34:10 2008
Info: Elapsed time: 00:00:04
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