state.v

来自「verilog写的分频程序,可以对输入的频率分频」· Verilog 代码 · 共 36 行

module state(clk,rst,st,sp,con,crst,hold);
input clk,rst,st,sp;
output con,crst,hold;

reg con,crst,hold;
always @(posedge clk or negedge rst)
begin 
    if (rst==0)
        begin 
           con=1'b0;
           crst=1'b1;
           hold=1'b0;
         end
    else 
	begin
		if(st)
		begin
		con=;
		crst=;
		hold=;
		end
		if(sp)
		begin
		con=;
		crst=;
		hold=;
		end
	end
end
endmodule