miaobiao.sim.rpt

verilog写的分频程序,可以对输入的频率分频

Simulator report for miaobiao
Thu Sep 25 00:27:55 2008
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Coverage Summary
  6. Complete 1/0-Value Coverage
  7. Missing 1-Value Coverage
  8. Missing 0-Value Coverage
  9. Simulator INI Usage
 10. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------+
; Simulator Summary ;
+------+------------+
; Type ; Value      ;
+------+------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                      ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Option                                                                                     ; Setting    ; Default Value ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Simulation mode                                                                            ; Timing     ; Timing        ;
; Start time                                                                                 ; 0 ns       ; 0 ns          ;
; Simulation results format                                                                  ; CVWF       ;               ;
; Vector input source                                                                        ; div.vwf    ;               ;
; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+------------------+
; Coverage Summary ;
+------+-----------+
; Type ; Value     ;
+------+-----------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------+
; Complete 1/0-Value Coverage                     ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
; Missing 1-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------+
; Missing 0-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Sep 25 00:27:54 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off miaobiao -c miaobiao
Info: Using vector source file "G:/tools/Quartus II/project/miaobiao/div.vwf"
Warning: Wrong node type and/or width for node "|dtlatch|q" in vector source file. Node in design is of type Bus and of width 16, but node in vector source file is of type 9-Level and of width 1.
Error: Can't simulate mismatched node types
Error: Quartus II Simulator was unsuccessful. 1 error, 1 warning
    Error: Peak virtual memory: 110 megabytes
    Error: Processing ended: Thu Sep 25 00:27:55 2008
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01