ir38k.vhd

来自「使用verilog语言控制CPLD通过红外收发器进行红外通讯」· VHDL 代码 · 共 44 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ir38k IS
 PORT(

      Res,clk,din:in std_logic;
      c_wave:out std_logic);
 END ir38k;

ARCHITECTURE behave OF ir38k IS
signal scan:std_logic;
Begin

div:process(clk,res)--分频为 38*3khz
variable divfre:std_logic_vector(7 downto 0):="00000000";
 Begin
if res='0'  then 
Divfre:=(others=>'0');
Scan<='0';
  elsif (clk 'event and clk ='1')
   then if divfre="11011100" 
           then 
              divfre:=(others=>'0');
              scan<=not scan;
        else divfre:=divfre+1;
        end if;
  end if;
 end process div;

i38k:process(scan,din,res)--实现占空比为1/3的功能。
variable t0:std_logic_vector(1 downto 0):="00";
Begin
If res='0' then
T0:="00";
 elsif scan'event and scan='1'
 then 
   if t0 = "10" then t0:="00";
   else t0:=t0+1;
   end if; 
 end if;
c_wave<=(not(t0(0) or t0(1))) and din;
end process i38k;
end behave;