keybuffer.v

我们的课程设计,三层电梯控制器模拟程序.用verilog HDL语言编写

module keybuffer(rst,
				up_key_1,
				up_key_2,
				down_key_2,
				down_key_3,
				to_key_1,
				to_key_2,
				to_key_3,
					
				up_rq_1,
				up_rq_2,
				down_rq_2,
				down_rq_3,
				to_rq_1,
				to_rq_2,
				to_rq_3,
				
				up_rq_1_done,
				up_rq_2_done,
				down_rq_2_done,
				down_rq_3_done,
				to_rq_1_done,
				to_rq_2_done,
				to_rq_3_done
				);
	input 		rst;			
	input		up_key_1;
	input		up_key_2;
	input		down_key_2;
	input		down_key_3;
	input		to_key_1;
	input		to_key_2;
	input		to_key_3;
				
	output		up_rq_1;
	output		up_rq_2;
	output		down_rq_2;
	output		down_rq_3;
	output		to_rq_1;
	output		to_rq_2;
	output		to_rq_3;
				
	input		up_rq_1_done;
	input		up_rq_2_done;
	input		down_rq_2_done;
	input		down_rq_3_done;
	input		to_rq_1_done;
	input		to_rq_2_done;
	input		to_rq_3_done;
	
	reg		up_rq_1;
	reg		up_rq_2;
	reg		down_rq_2;
	reg		down_rq_3;
	reg		to_rq_1;
	reg		to_rq_2;
	reg		to_rq_3;
	always @(up_key_1 or up_rq_1_done or rst)begin
		if(up_rq_1_done | ~rst)
			up_rq_1 <= 1'b0;
		else if(up_key_1)
			up_rq_1 <= 1'b1;
	end
	
	always @(up_key_2 or up_rq_2_done or rst)begin
		if(up_rq_2_done | ~rst)
			up_rq_2 <= 1'b0;
		else if(up_key_2)
			up_rq_2 <= 1'b1;
	end
	
	always @(down_key_2 or down_rq_2_done or rst)begin
		if(down_rq_2_done | ~rst)
			down_rq_2 <= 1'b0;
		else if(down_key_2)
			down_rq_2 <= 1'b1;
	end
	
	always @(down_key_3 or down_rq_3_done or rst)begin
		if(down_rq_3_done | ~rst)
			down_rq_3 <= 1'b0;
		else if(down_key_3)
			down_rq_3 <= 1'b1;
	end
	
	always @(to_key_1 or to_rq_1_done or rst)begin
		if(to_rq_1_done | ~rst)
			to_rq_1 <= 1'b0;
		else if(to_key_1)
			to_rq_1 <= 1'b1;
	end
	always @(to_key_2 or to_rq_2_done or rst)begin
		if(to_rq_2_done | ~rst)
			to_rq_2 <= 1'b0;
		else if(to_key_2)
			to_rq_2 <= 1'b1;
	end
	always @(to_key_3 or to_rq_3_done or rst)begin
		if(to_rq_3_done | ~rst)
			to_rq_3 <= 1'b0;
		else if(to_key_3)
			to_rq_3 <= 1'b1;
	end
endmodule