pcore.v

基于SDRAM总线的加速部件核心和相关论文说明

module pcore(
sysclk,
clkdiv_i,
rst_i,
read_i,
write_i,
addr_i,
din,
dout,
dmask_i,
extin,
extout,
extctrl_o
);
//---------------input and output claim
input           sysclk;
input           clkdiv_i;
input           rst_i;
input           read_i;
input           write_i;
input [13:0]    addr_i;
input [63:0]    din;
input [63:0]    dmask_i;
input [25:0]    extin;

output[63:0]    dout;
output[25:0]    extout;
output[25:0]    extctrl_o;




//-----------------------reg claim
reg   [2:0]     state;
reg   [2:0]     next_state;

reg   [7:0]     addr_cnt;


//-----------------------wire claim
wire            GND;
wire            VDD;
wire  [15:0]    dia;
wire            cnt_en;
wire  [15:0]    dib;

wire  [1 :0]    st;
//-----------parameter claim
parameter       STATE_ONE = 3'b001,
                STATE_TWO = 3'b010,
                STATE_TRI = 3'b100;
                
parameter       TARGET_ADDR1 = 8'hff,
                TARGET_ADDR2 = 8'hff;

//-----------------------main part
assign GND = 1'b0;
assign VDD = 1'b1;

//-------------------实例化
 ram1 RAMB4_S16(
           write_i        ,
           VDD            ,
           rst_i          ,
           sysclk         ,
           addr_i [7 :0]  ,
           din    [15:0]  ,
           dout   [15:0]  
           );

assign cnt_en = state == STATE_TRI ? 1 : 0;
           
always@(posedge clkdiv_i or posedge rst_i)
begin
      if (rst_i)
           addr_cnt <= 7'b0000000;
      else
      begin
           if( cnt_en )
              addr_cnt <= addr_cnt + 1;           
           else 
              addr_cnt <= addr_cnt;
      end
end    
       
assign  dia = { addr_cnt , 8'b01011010 };

ram2 RAMB4_S16_S16(
       cnt_en           ,
       VDD              ,
       rst_i            ,
       clkdiv_i         ,
       addr_cnt         ,
       dia              ,
       dib              ,//-----------no used  
       GND              ,
       VDD              ,
       rst_i            ,
       sysclk           ,
       addr_i [ 7: 0]   ,
       dia              ,
       dout   [31:16]          
       );
       
//------------------------main fsm

always@(state or write_i or addr_r)
begin
     case(state)
     STATE_ONE:
             begin
             st         =  2'b00;
             next_state =  STATE_TWO;
             end             
     STATE_TWO:
             begin
             st              =  2'b01;
             if(write_i == 1 && addr_i == TARGET_ADDR1)
                  next_state = STATE_TRI;
             else
                  next_state = STATE_TWO;
             end       
     STATE_TRI:
             begin
             st              = 2'b10;
             if(write_i == 1 && addr_i == TARGET_ADDR2)
                  next_state = STATE_TWO;
             else
                  next_state = STATE_TRI;                    
             end
             
     default: 
                  begin
                  st         = 2'b10;
                  next_state = STATE_ONE; 
                  end
     endcase
end
     
always@(posedge sysclk or posedge rst_i)
begin
    if(rst_i)
        state <= STATE_ONE;
    else
        state <= next_state;
end     
//-------------------output
assign dout[63:34] = din[63:34];
assign dout[33:32] = st;

assign extout[0]     = clkdiv_i;
assign extout[1]     = rst_i;
assign extout[2]     = read_i;
assign extout[3]     = write_i;
assign extout[5:4]   = st;
assign extout[13:6]  = addr_i[7:0];
assign extout[14]    = cnt_en;
assign extout[22:15] = addr_cnt
assign extout[25:23] = 3'b000;

assign extctrl_o       = 26'h0000000;

endmodule;