fft_bit_reverse_top.vhd

OFDM的fpga实现

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--
library ieee;
use ieee.std_logic_1164.all;
library auk_dspip_r22sdf_lib;

entity fft_bit_reverse_top is
  port (
    clk          : in  std_logic;
    reset_n      : in  std_logic;
    fftpts_in    : in  std_logic_vector(11 downto 0);
    fftpts_out   : out  std_logic_vector(11 downto 0);
    inverse      : in  std_logic;
    sink_ready   : out std_logic;
    sink_valid   : in  std_logic;
    sink_real    : in  std_logic_vector(16 -1 downto 0);
    sink_imag    : in  std_logic_vector(16 - 1 downto 0);
    sink_sop     : in  std_logic;
    sink_eop     : in  std_logic;
    sink_error   : in std_logic_vector(1 downto 0);
    source_error : out std_logic_vector(1 downto 0);
    source_ready : in  std_logic;
    source_valid : out std_logic;
    source_real  : out std_logic_vector(31 - 1 downto 0);
    source_imag  : out std_logic_vector(31 - 1 downto 0);
    source_sop   : out std_logic;
    source_eop   : out std_logic);
end entity fft_bit_reverse_top;



architecture str of fft_bit_reverse_top is


  signal r22sdf_ready : std_logic;
  signal r22sdf_valid : std_logic;
  signal r22sdf_real  : std_logic_vector(31 - 1 downto 0);
  signal r22sdf_imag  : std_logic_vector(31 - 1 downto 0);
  signal r22sdf_sop   : std_logic;
  signal r22sdf_eop   : std_logic;
  signal r22sdf_error   : std_logic_vector(1 downto 0);
  signal sink_ready_s : std_logic;
  signal curr_fftpts : std_logic_vector(11 downto 0);


  component fft is
    port (
      clk          : in  std_logic;
      reset_n      : in  std_logic;
      fftpts_in    : in  std_logic_vector (11 downto 0);
      fftpts_out   : out  std_logic_vector (11 downto 0);
      inverse      : in  std_logic;
      sink_valid   : in  std_logic;
      sink_sop     : in  std_logic;
      sink_eop     : in  std_logic;
      sink_real    : in  std_logic_vector (16 - 1 downto 0);
      sink_imag    : in  std_logic_vector (16 - 1  downto 0);
      sink_error   : in std_logic_vector(1 downto 0);
      source_error : out std_logic_vector(1 downto 0);
      source_ready : in  std_logic;
      sink_ready   : out std_logic;
      source_sop   : out std_logic;
      source_eop   : out std_logic;
      source_valid : out std_logic;
      source_real  : out std_logic_vector (31 - 1 downto 0);
      source_imag  : out std_logic_vector (31 - 1 downto 0)
      ); 
 end component fft;

  component auk_dspip_bit_reverse_top_fft_71 is
    generic (
      MAX_BLKSIZE_g : natural;
      DATAWIDTH_g   : natural);
    port (
      clk          : in  std_logic;
      reset_n      : in  std_logic;
      blksize_in   : in  std_logic_vector(11 downto 0);
      blksize_out  : out  std_logic_vector(11 downto 0);
      sink_ready   : out std_logic;
      sink_valid   : in  std_logic;
      sink_real    : in  std_logic_vector(31 - 1 downto 0);
      sink_imag    : in  std_logic_vector(31 - 1 downto 0);
      sink_sop     : in  std_logic;
      sink_eop     : in  std_logic;
      sink_error   : in std_logic_vector(1 downto 0);
      source_error : out std_logic_vector(1 downto 0);
      source_ready : in  std_logic;
      source_valid : out std_logic;
      source_real  : out std_logic_vector(31 - 1 downto 0);
      source_imag  : out std_logic_vector(31 - 1 downto 0);
      source_sop   : out std_logic;
      source_eop   : out std_logic);
  end component auk_dspip_bit_reverse_top_fft_71;
  
begin  -- architecture str

  sink_ready <= sink_ready_s;

 fft_inst :  fft
  port map (
      clk          => clk,
      reset_n      => reset_n,
      fftpts_in    => fftpts_in,
      fftpts_out   => curr_fftpts,
      inverse      => inverse,
      sink_ready   => sink_ready_s,
      sink_valid   => sink_valid,
      sink_real    => sink_real,
      sink_imag    => sink_imag,
      sink_sop     => sink_sop,
      sink_eop     => sink_eop,
      sink_error   => sink_error,
      source_error => r22sdf_error,
      source_ready => r22sdf_ready,
      source_valid => r22sdf_valid,
      source_real  => r22sdf_real,
      source_imag  => r22sdf_imag,
      source_sop   => r22sdf_sop,
      source_eop   => r22sdf_eop);

  bitreverse_i : auk_dspip_bit_reverse_top_fft_71
    generic map (
      MAX_BLKSIZE_g => 2048,
      DATAWIDTH_g   => 31)
    port map (
      clk          => clk,
      reset_n      => reset_n,
      blksize_in   => curr_fftpts,
      blksize_out  => fftpts_out,
      sink_ready   => r22sdf_ready,
      sink_valid   => r22sdf_valid,
      sink_real    => r22sdf_real,
      sink_imag    => r22sdf_imag,
      sink_sop     => r22sdf_sop,
      sink_eop     => r22sdf_eop,
      sink_error   => r22sdf_error,
      source_error => source_error,
      source_ready => source_ready,
      source_valid => source_valid,
      source_real  => source_real,
      source_imag  => source_imag,
      source_sop   => source_sop,
      source_eop   => source_eop);


end architecture str;