ofdm_kernel_tx.vhd

OFDM的fpga实现

-- ================================================================================
-- (c) 2007 Altera Corporation. All rights reserved.
-- These design examples may only be used within Altera Corporation devices and remain 
-- the property of Altera. They are being provided on "as-is" basis and as an accommodation; 
-- therefore, all warranties, representations, or guarantees of any kind (whether express, 
-- implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, 
-- or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, 
-- suggest, or require that these examples be used in combination with any other product not provided 
-- by Altera.
-- ================================================================================
-- 
-- Filename    : ofdm_kernel_Tx.vhd
--
-- Description : Performs IFFT and addition of Cyclic Prefix to an OFDM symbol.
--               Support for run time change of FFT sizes of 16, 32, 64, 128,
--               256, 512, 1024 and 2048.  Support for run time change of
--               Cyclic Prefix sizes of arbitrary value.
--
--               Purpose to be used in Base Station downlink transmission (Tx)
--               for OFDM systems.
--
--               Input/Output Interfaces:
--               Avalon Streaming Interface 
--
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;

entity ofdm_kernel_Tx is
  generic
    (
      DFFTOUTWIDTH : natural := 31;
      DFFTINWIDTH  : natural := 16;
      DOUTWIDTH    : natural := 32;
      MWIDTH       : natural := 64;
      MADDR_WIDTH  : natural := 12;
      CPWIDTH      : natural := 10;
      MDEPTH       : natural := 4096;
      NWIDTH       : natural := 12
      );

  port
    (
      clk_f   : in std_logic;
      clk_s   : in std_logic;
      rst_f_n : in std_logic;
      rst_s_n : in std_logic;

      -- Control 
      L : in std_logic_vector (CPWIDTH - 1 downto 0);

      Lout : out std_logic_vector (CPWIDTH - 1 downto 0);

      N    : in  std_logic_vector (NWIDTH - 1 downto 0);
      Nout : out std_logic_vector(NWIDTH -1 downto 0);
      inv  : in  std_logic;             -- '1' for IFFT

      -- Avalon Streaming Data Sink Input Interface
      din_valid : in  std_logic;
      din_real  : in  std_logic_vector (DFFTINWIDTH - 1 downto 0);
      din_imag  : in  std_logic_vector (DFFTINWIDTH - 1 downto 0);
      din_sop   : in  std_logic;
      din_eop   : in  std_logic;
      din_error : in  std_logic_vector(1 downto 0);
      din_ready : out std_logic;

      -- Avalon Streaming Source Interface

      dout_ready : in std_logic;

      dout_valid : out std_logic;
      dout_sop   : out std_logic;
      dout_eop   : out std_logic;
      dout_real  : out std_logic_vector (DOUTWIDTH - 1 downto 0);
      dout_imag  : out std_logic_vector (DOUTWIDTH - 1 downto 0)

      );
end ofdm_kernel_Tx;

architecture rtl of ofdm_kernel_Tx is

  -----------------------------------------------------------------------------
  -- COMPONENT DECLARATIONS
  -----------------------------------------------------------------------------
  component fifobuff is
    generic (
      DWIDTH : natural);
    port
      (
        clock : in  std_logic;
        data  : in  std_logic_vector (DWIDTH - 1 downto 0);
        rdreq : in  std_logic;
        wrreq : in  std_logic;
        q     : out std_logic_vector (DWIDTH - 1 downto 0)
        );
  end component fifobuff;

  component fft is
    port (
      clk          : in  std_logic;
      reset_n      : in  std_logic;
      fftpts_in    : in  std_logic_vector (NWIDTH - 1 downto 0);
      inverse      : in  std_logic;
      sink_valid   : in  std_logic;
      sink_sop     : in  std_logic;
      sink_eop     : in  std_logic;
      sink_real    : in  std_logic_vector (DFFTINWIDTH - 1 downto 0);
      sink_imag    : in  std_logic_vector (DFFTINWIDTH - 1 downto 0);
      source_ready : in  std_logic;
      sink_ready   : out std_logic;
      sink_error   : in  std_logic_vector(1 downto 0);
      source_error : out std_logic_vector(1 downto 0);
      source_sop   : out std_logic;
      source_eop   : out std_logic;
      source_valid : out std_logic;
      fftpts_out   : out std_logic_vector(NWIDTH -1 downto 0);
      source_real  : out std_logic_vector (DFFTOUTWIDTH - 1 downto 0);
      source_imag  : out std_logic_vector (DFFTOUTWIDTH - 1 downto 0)
      ); 
  end component fft;


  component add_cyclic_prefix
    generic
      (
        DFFTOUTWIDTH : natural := 31;
        DOUTWIDTH    : natural := 32;
        NWIDTH       : natural := 12;
        MWIDTH       : natural := 64;
        MADDR_WIDTH  : natural := 12;
        MDEPTH       : natural := 4096;
        CPWIDTH      : natural := 10
        );

    port
      (
        clk_in    : in std_logic;
        clk_out   : in std_logic;
        rst_in_n  : in std_logic;
        rst_out_n : in std_logic;

        -- Control 
        L    : in  std_logic_vector (CPWIDTH - 1 downto 0);
        N    : in  std_logic_vector(NWIDTH - 1 downto 0);
        Nout : out std_logic_vector(NWIDTH - 1 downto 0);
        Lout : out std_logic_vector (CPWIDTH - 1 downto 0);

        -- Avalon Streaming Input Interface
        in_real : in std_logic_vector (DFFTOUTWIDTH - 1 downto 0);
        in_imag : in std_logic_vector (DFFTOUTWIDTH - 1 downto 0);

        in_valid : in  std_logic;
        in_sop   : in  std_logic;
        in_eop   : in  std_logic;
        in_ready : out std_logic;

        out_ready : in std_logic;

        out_valid : out std_logic;
        out_sop   : out std_logic;
        out_eop   : out std_logic;
        out_real  : out std_logic_vector (DOUTWIDTH - 1 downto 0);
        out_imag  : out std_logic_vector (DOUTWIDTH - 1 downto 0);

        -- Interface with memory
        mem_dout : in std_logic_vector (MWIDTH - 1 downto 0);

        mem_din    : out    std_logic_vector (MWIDTH - 1 downto 0);
        mem_wren   : out    std_logic := '1';
        mem_wraddr : buffer std_logic_vector (MADDR_WIDTH - 1 downto 0);
        mem_rdaddr : buffer std_logic_vector (MADDR_WIDTH - 1 downto 0)
        );
  end component;

  component cp_mem
    generic
      (
        MWIDTH      : natural := 64;
        MDEPTH      : natural := 4096;
        MADDR_WIDTH : natural := 12
        );
    port
      (
        data      : in  std_logic_vector (MWIDTH - 1 downto 0);
        wren      : in  std_logic := '1';
        wraddress : in  std_logic_vector (MADDR_WIDTH - 1 downto 0);
        rdaddress : in  std_logic_vector (MADDR_WIDTH - 1 downto 0);
        wrclock   : in  std_logic;
        rdclock   : in  std_logic;
        rd_aclr   : in  std_logic := '0';
        q         : out std_logic_vector (MWIDTH - 1 downto 0)
        );
  end component;
  -----------------------------------------------------------------------------
  -- SIGNAL DECLARATIONS
  -----------------------------------------------------------------------------
  signal rst_f : std_logic;
  signal rst_s : std_logic;

  signal fft_source_real  : std_logic_vector (DFFTOUTWIDTH - 1 downto 0);
  signal fft_source_imag  : std_logic_vector (DFFTOUTWIDTH - 1 downto 0);
--  signal fft_source_real_r                    : std_logic_vector (DOUTWIDTH - 1 downto 0);
--  signal fft_source_imag_r                    : std_logic_vector (DOUTWIDTH - 1 downto 0);
  signal fft_source_ready : std_logic;
  signal fft_source_sop   : std_logic;
  signal N_val            : std_logic_vector(NWIDTH - 1 downto 0);
  signal fft_source_eop   : std_logic;
  signal fft_source_error : std_logic_vector (1 downto 0);
  signal fft_source_valid : std_logic;
  signal fft_sink_ready   : std_logic;

  signal Lq, Lcp : std_logic_vector (CPWIDTH -1 downto 0);
--  signal inv_i          : std_logic := '1';

  signal mem_din    : std_logic_vector (MWIDTH - 1 downto 0);
  signal mem_wren   : std_logic := '1';
  signal mem_wraddr : std_logic_vector (MADDR_WIDTH - 1 downto 0);
  signal mem_rdaddr : std_logic_vector (MADDR_WIDTH - 1 downto 0);
  signal mem_dout   : std_logic_vector (MWIDTH - 1 downto 0);

  signal fifo_rreq : std_logic;
  signal fifo_wreq : std_logic;

  signal fifo_start_out : std_logic;

begin
  rst_f <= not(rst_f_n);
  rst_s <= not(rst_f_n);
--  inv_i <= '1';                         -- for Tx FFT Megacore
  -- only performs IFFT
  process (clk_f, rst_f_n)
  begin
    if (rst_f_n = '0') then
      fifo_start_out <= '0';
    elsif rising_edge(clk_f) then
      if fifo_rreq = '1' then
        fifo_start_out <= '1';
      else
        fifo_start_out <= fifo_start_out;
      end if;
    end if;
  end process;

  fifo_rreq <= (fft_source_sop and fft_source_valid and fft_source_ready);
  fifo_wreq <= (din_sop and din_valid and fft_sink_ready);

  -----------------------------------------------------------------------------
  -- Instantiating fifo for L buffer
  -----------------------------------------------------------------------------

  Lbuff_inst : fifobuff
    generic map (
      DWIDTH => CPWIDTH)
    port map (
      clock => clk_f,
      data  => L,
      wrreq => fifo_wreq,
      rdreq => fifo_rreq,
      q     => Lq); 


  Lcp <= Lq when fifo_start_out = '1' else
         (others => '0');

  -----------------------------------------------------------------------------
  -- Instantiating FFT submodule
  --
  -- Performs IFFT for Tx 
  -- Megacore configured for Variable Streaming mode
  -----------------------------------------------------------------------------
  din_ready <= fft_sink_ready;

  fft_inst : fft
    port map
    (
      clk          => clk_f,
      reset_n      => rst_f_n,
      fftpts_in    => N,
      inverse      => inv,
      sink_sop     => din_sop,
      sink_eop     => din_eop,
      sink_valid   => din_valid,
      sink_real    => din_real,
      sink_imag    => din_imag,
      sink_ready   => fft_sink_ready,
      sink_error   => din_error,
      source_real  => fft_source_real,
      source_imag  => fft_source_imag,
      source_sop   => fft_source_sop,
      source_eop   => fft_source_eop,
      source_ready => fft_source_ready,
      source_error => fft_source_error,
      fftpts_out   => N_val,
      source_valid => fft_source_valid
      );

  -----------------------------------------------------------------------------
  -- Instantiating Add Cyclic Prefix submodule
  --
  -- For Tx ONLY, adds cyclic prefix to IFFT output. Outputs continous 
  -- stream of valid data.
  -----------------------------------------------------------------------------
  
  add_cyclic_prefix_u : add_cyclic_prefix
    generic map
    (
      DFFTOUTWIDTH => DFFTOUTWIDTH,
      DOUTWIDTH    => DOUTWIDTH,
      NWIDTH       => NWIDTH,
      MWIDTH       => MWIDTH,
      CPWIDTH      => CPWIDTH,
      MDEPTH       => MDEPTH,
      MADDR_WIDTH  => MADDR_WIDTH
      )

    port map
    (
      clk_in     => clk_f,
      clk_out    => clk_s,
      rst_in_n   => rst_f_n,
      rst_out_n  => rst_s_n,
      -- Control 
      L          => Lcp,
      N          => N_val,
      Nout       => Nout,
      Lout       => Lout,
      -- input interface
      in_real    => fft_source_real,
      in_imag    => fft_source_imag,
      in_valid   => fft_source_valid,
      in_sop     => fft_source_sop,
      in_eop     => fft_source_eop,
      in_ready   => fft_source_ready,
      -- Output Interface 
      out_ready  => dout_ready,
      out_valid  => dout_valid,
      out_sop    => dout_sop,
      out_eop    => dout_eop,
      out_real   => dout_real,
      out_imag   => dout_imag,
      -- Interface with memory
      mem_dout   => mem_dout,
      mem_din    => mem_din,
      mem_wren   => mem_wren,
      mem_wraddr => mem_wraddr,
      mem_rdaddr => mem_rdaddr
      );
  -----------------------------------------------------------------------------
  -- Instantiating Dual Port RAM to store data to be fed into FFT Megacore.
  -- 
  -- Input data is fed from IFFT Megacore output using fast clk.
  -- Read from memory with slow clk to have cyclic prefix added.
  -----------------------------------------------------------------------------
  cp_mem_u : cp_mem
    generic map
    (
      MWIDTH      => MWIDTH,
      MDEPTH      => MDEPTH,
      MADDR_WIDTH => MADDR_WIDTH
      )
    port map
    (
      data      => mem_din,
      wren      => mem_wren,
      wraddress => mem_wraddr,
      rdaddress => mem_rdaddr,
      wrclock   => clk_f,
      rdclock   => clk_s,
      rd_aclr   => rst_s,
      q         => mem_dout
      );

-----------------------------------------------------------------------------
end rtl;