defxx.h

powerpc内核mpc8241linux系统下net驱动程序

#define PI_TYPE_0_STAT_V_20MS			6	
#define PI_TYPE_0_STAT_V_CSR_CMD_DONE	5
#define PI_TYPE_0_STAT_V_STATE_CHANGE	4
#define PI_TYPE_0_STAT_V_XMT_FLUSH		3
#define PI_TYPE_0_STAT_V_NXM			2
#define PI_TYPE_0_STAT_V_PM_PAR_ERR		1
#define PI_TYPE_0_STAT_V_BUS_PAR_ERR	0

/* Register definition structures are defined for both big and little endian systems */

#ifndef  BIG_ENDIAN

/* Little endian format of Type 1 Producer register */

typedef union
	{
	PI_UINT32	lword;
	struct
		{
		PI_UINT8	prod;
		PI_UINT8	comp;
		PI_UINT8	mbz_1;
		PI_UINT8	mbz_2;
		} index;
	} PI_TYPE_1_PROD_REG;

/* Little endian format of Type 2 Producer register */

typedef union
	{
	PI_UINT32	lword;
	struct
		{
		PI_UINT8	rcv_prod;
		PI_UINT8	xmt_prod;
		PI_UINT8	rcv_comp;
		PI_UINT8	xmt_comp;
		} index;
	} PI_TYPE_2_PROD_REG;

/* Little endian format of Type 1 Consumer Block longword */

typedef union
	{
	PI_UINT32	lword;
	struct
		{
		PI_UINT8	cons;
		PI_UINT8	res0;
		PI_UINT8	res1;
		PI_UINT8	res2;
		} index;
	} PI_TYPE_1_CONSUMER;

/* Little endian format of Type 2 Consumer Block longword */

typedef union
	{
	PI_UINT32	lword;
	struct
		{
		PI_UINT8	rcv_cons;
		PI_UINT8	res0;
		PI_UINT8	xmt_cons;
		PI_UINT8	res1;
		} index;
	} PI_TYPE_2_CONSUMER;

#else

/* Big endian format of Type 1 Producer register */

typedef union
	{
	PI_UINT32	lword;
	struct
		{
		PI_UINT8	mbz_2;
		PI_UINT8	mbz_1;
		PI_UINT8	comp;
		PI_UINT8	prod;
		} index;
	} PI_TYPE_1_PROD_REG;

/* Big endian format of Type 2 Producer register */

typedef union
	{
	PI_UINT32	lword;
	struct
		{
		PI_UINT8	xmt_comp;
		PI_UINT8	rcv_comp;
		PI_UINT8	xmt_prod;
		PI_UINT8	rcv_prod;
		} index;
	} PI_TYPE_2_PROD_REG;

/* Big endian format of Type 1 Consumer Block longword */

typedef union
	{
	PI_UINT32	lword;
	struct
		{
		PI_UINT8	res2;
		PI_UINT8	res1;
		PI_UINT8	res0;
		PI_UINT8	cons;
		} index;
	} PI_TYPE_1_CONSUMER;

/* Big endian format of Type 2 Consumer Block longword */

typedef union
	{
	PI_UINT32	lword;
	struct
		{
		PI_UINT8	res1;
		PI_UINT8	xmt_cons;
		PI_UINT8	res0;
		PI_UINT8	rcv_cons;
		} index;
	} PI_TYPE_2_CONSUMER;

#endif	/* #ifndef BIG_ENDIAN */

/* Define EISA controller register offsets */

#define PI_ESIC_K_BURST_HOLDOFF			0x040
#define PI_ESIC_K_SLOT_ID            	0xC80
#define PI_ESIC_K_SLOT_CNTRL			0xC84
#define PI_ESIC_K_MEM_ADD_CMP_0     	0xC85
#define PI_ESIC_K_MEM_ADD_CMP_1     	0xC86
#define PI_ESIC_K_MEM_ADD_CMP_2     	0xC87
#define PI_ESIC_K_MEM_ADD_HI_CMP_0  	0xC88
#define PI_ESIC_K_MEM_ADD_HI_CMP_1  	0xC89
#define PI_ESIC_K_MEM_ADD_HI_CMP_2  	0xC8A
#define PI_ESIC_K_MEM_ADD_MASK_0     	0xC8B
#define PI_ESIC_K_MEM_ADD_MASK_1     	0xC8C
#define PI_ESIC_K_MEM_ADD_MASK_2     	0xC8D
#define PI_ESIC_K_MEM_ADD_LO_CMP_0  	0xC8E
#define PI_ESIC_K_MEM_ADD_LO_CMP_1  	0xC8F
#define PI_ESIC_K_MEM_ADD_LO_CMP_2  	0xC90
#define PI_ESIC_K_IO_CMP_0_0			0xC91
#define PI_ESIC_K_IO_CMP_0_1			0xC92
#define PI_ESIC_K_IO_CMP_1_0			0xC93
#define PI_ESIC_K_IO_CMP_1_1			0xC94
#define PI_ESIC_K_IO_CMP_2_0			0xC95
#define PI_ESIC_K_IO_CMP_2_1			0xC96
#define PI_ESIC_K_IO_CMP_3_0			0xC97
#define PI_ESIC_K_IO_CMP_3_1			0xC98
#define PI_ESIC_K_IO_ADD_MASK_0_0    	0xC99
#define PI_ESIC_K_IO_ADD_MASK_0_1    	0xC9A
#define PI_ESIC_K_IO_ADD_MASK_1_0    	0xC9B
#define PI_ESIC_K_IO_ADD_MASK_1_1    	0xC9C
#define PI_ESIC_K_IO_ADD_MASK_2_0    	0xC9D
#define PI_ESIC_K_IO_ADD_MASK_2_1    	0xC9E
#define PI_ESIC_K_IO_ADD_MASK_3_0    	0xC9F
#define PI_ESIC_K_IO_ADD_MASK_3_1    	0xCA0
#define PI_ESIC_K_MOD_CONFIG_1			0xCA1
#define PI_ESIC_K_MOD_CONFIG_2			0xCA2
#define PI_ESIC_K_MOD_CONFIG_3			0xCA3
#define PI_ESIC_K_MOD_CONFIG_4			0xCA4
#define PI_ESIC_K_MOD_CONFIG_5    		0xCA5
#define PI_ESIC_K_MOD_CONFIG_6			0xCA6
#define PI_ESIC_K_MOD_CONFIG_7			0xCA7
#define PI_ESIC_K_DIP_SWITCH         	0xCA8
#define PI_ESIC_K_IO_CONFIG_STAT_0   	0xCA9
#define PI_ESIC_K_IO_CONFIG_STAT_1   	0xCAA
#define PI_ESIC_K_DMA_CONFIG         	0xCAB
#define PI_ESIC_K_INPUT_PORT         	0xCAC
#define PI_ESIC_K_OUTPUT_PORT        	0xCAD
#define PI_ESIC_K_FUNCTION_CNTRL		0xCAE
#define PI_ESIC_K_CSR_IO_LEN			PI_ESIC_K_FUNCTION_CNTRL+1	/* always last reg + 1 */

/* Define the value all drivers must write to the function control register. */

#define PI_ESIC_K_FUNCTION_CNTRL_IO_ENB	0x03

/* Define the bits in the slot control register. */

#define PI_SLOT_CNTRL_M_RESET		0x04	/* Don't use.       */
#define PI_SLOT_CNTRL_M_ERROR		0x02	/* Not implemented. */
#define PI_SLOT_CNTRL_M_ENB			0x01	/* Must be set.     */

/* Define the bits in the burst holdoff register. */

#define PI_BURST_HOLDOFF_M_HOLDOFF	0xFC
#define PI_BURST_HOLDOFF_M_RESERVED	0x02
#define PI_BURST_HOLDOFF_M_MEM_MAP	0x01

#define PI_BURST_HOLDOFF_V_HOLDOFF	2
#define PI_BURST_HOLDOFF_V_RESERVED	1
#define PI_BURST_HOLDOFF_V_MEM_MAP	0

/*
 * Define the fields in the IO Compare registers.
 * The driver must initialize the slot field with the slot ID shifted by the
 * amount shown below.
 */

#define PI_IO_CMP_V_SLOT		4

/* Define the fields in the Interrupt Channel Configuration and Status reg */

#define PI_CONFIG_STAT_0_M_PEND			0x80
#define PI_CONFIG_STAT_0_M_RES_1		0x40
#define PI_CONFIG_STAT_0_M_IREQ_OUT		0x20
#define PI_CONFIG_STAT_0_M_IREQ_IN		0x10
#define PI_CONFIG_STAT_0_M_INT_ENB		0x08
#define PI_CONFIG_STAT_0_M_RES_0		0x04
#define PI_CONFIG_STAT_0_M_IRQ			0x03

#define PI_CONFIG_STAT_0_V_PEND			7
#define PI_CONFIG_STAT_0_V_RES_1		6
#define PI_CONFIG_STAT_0_V_IREQ_OUT		5
#define PI_CONFIG_STAT_0_V_IREQ_IN		4
#define PI_CONFIG_STAT_0_V_INT_ENB		3
#define PI_CONFIG_STAT_0_V_RES_0		2
#define PI_CONFIG_STAT_0_V_IRQ			0

#define PI_CONFIG_STAT_0_IRQ_K_9		0
#define PI_CONFIG_STAT_0_IRQ_K_10		1
#define PI_CONFIG_STAT_0_IRQ_K_11		2
#define PI_CONFIG_STAT_0_IRQ_K_15		3

/* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */

#define DEFEA_PRODUCT_ID	0x0030A310		/* DEC product 300 (no rev)	*/
#define DEFEA_PROD_ID_1		0x0130A310		/* DEC product 300, rev 1	*/
#define DEFEA_PROD_ID_2		0x0230A310		/* DEC product 300, rev 2	*/
#define DEFEA_PROD_ID_3		0x0330A310		/* DEC product 300, rev 3	*/

/**********************************************/
/* Digital PFI Specification v1.0 Definitions */
/**********************************************/

/* PCI Configuration Space Constants */

#define PFI_K_LAT_TIMER_DEF			0x88	/* def max master latency timer */
#define PFI_K_LAT_TIMER_MIN			0x20	/* min max master latency timer */
#define PFI_K_CSR_MEM_LEN			0x80	/* 128 bytes */
#define PFI_K_CSR_IO_LEN			0x80	/* 128 bytes */
#define PFI_K_PKT_MEM_LEN			0x10000	/* 64K bytes */

/* PFI Register Offsets (starting at PDQ Register Base Address) */

#define PFI_K_REG_RESERVED_0		 0X00000038
#define PFI_K_REG_RESERVED_1		 0X0000003C
#define PFI_K_REG_MODE_CTRL			 0X00000040
#define PFI_K_REG_STATUS			 0X00000044
#define PFI_K_REG_FIFO_WRITE		 0X00000048
#define PFI_K_REG_FIFO_READ			 0X0000004C

/* PFI Mode Control Register Constants */

#define PFI_MODE_M_RESERVED			 0XFFFFFFF0
#define PFI_MODE_M_TGT_ABORT_ENB	 0X00000008
#define PFI_MODE_M_PDQ_INT_ENB		 0X00000004
#define PFI_MODE_M_PFI_INT_ENB		 0X00000002
#define PFI_MODE_M_DMA_ENB			 0X00000001

#define PFI_MODE_V_RESERVED			 4
#define PFI_MODE_V_TGT_ABORT_ENB	 3
#define PFI_MODE_V_PDQ_INT_ENB		 2
#define PFI_MODE_V_PFI_INT_ENB		 1
#define PFI_MODE_V_DMA_ENB			 0

#define PFI_MODE_K_ALL_DISABLE		 0X00000000

/* PFI Status Register Constants */

#define PFI_STATUS_M_RESERVED		 0XFFFFFFC0
#define PFI_STATUS_M_PFI_ERROR		 0X00000020		/* only valid in rev 1 or later PFI */
#define PFI_STATUS_M_PDQ_INT		 0X00000010
#define PFI_STATUS_M_PDQ_DMA_ABORT	 0X00000008
#define PFI_STATUS_M_FIFO_FULL		 0X00000004
#define PFI_STATUS_M_FIFO_EMPTY		 0X00000002
#define PFI_STATUS_M_DMA_IN_PROGRESS 0X00000001

#define PFI_STATUS_V_RESERVED		 6
#define PFI_STATUS_V_PFI_ERROR		 5				/* only valid in rev 1 or later PFI */
#define PFI_STATUS_V_PDQ_INT		 4
#define PFI_STATUS_V_PDQ_DMA_ABORT	 3
#define PFI_STATUS_V_FIFO_FULL		 2
#define PFI_STATUS_V_FIFO_EMPTY		 1
#define PFI_STATUS_V_DMA_IN_PROGRESS 0

#define DFX_MAX_EISA_SLOTS		16			/* maximum number of EISA slots to scan */
#define DFX_MAX_NUM_BOARDS		8			/* maximum number of adapters supported */

#define DFX_BUS_TYPE_PCI		0			/* type code for DEC FDDIcontroller/PCI */
#define DFX_BUS_TYPE_EISA		1			/* type code for DEC FDDIcontroller/EISA */

#define DFX_FC_PRH2_PRH1_PRH0	0x54003820	/* Packet Request Header bytes + FC */
#define DFX_PRH0_BYTE			0x20		/* Packet Request Header byte 0 */
#define DFX_PRH1_BYTE			0x38		/* Packet Request Header byte 1 */
#define DFX_PRH2_BYTE			0x00		/* Packet Request Header byte 2 */

/* Driver routine status (return) codes */

#define DFX_K_SUCCESS			0			/* routine succeeded */
#define DFX_K_FAILURE			1			/* routine failed */
#define DFX_K_OUTSTATE			2			/* bad state for command */
#define DFX_K_HW_TIMEOUT		3			/* command timed out */

/* Define LLC host receive buffer min/max/default values */

#define RCV_BUFS_MIN	2					/* minimum pre-allocated receive buffers */
#define RCV_BUFS_MAX	32					/* maximum pre-allocated receive buffers */
#define RCV_BUFS_DEF	8					/* default pre-allocated receive buffers */

/* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */

#define RCV_BUFF_K_DESCR	0				/* four byte FMC descriptor */
#define RCV_BUFF_K_PADDING	4				/* three null bytes */
#define RCV_BUFF_K_FC		7				/* one byte frame control */
#define RCV_BUFF_K_DA		8				/* six byte destination address */
#define RCV_BUFF_K_SA		14				/* six byte source address */
#define RCV_BUFF_K_DATA		20				/* offset to start of packet data */

/* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */

#define XMT_BUFF_K_FC		0				/* one byte frame control */
#define XMT_BUFF_K_DA		1				/* six byte destination address */
#define XMT_BUFF_K_SA		7				/* six byte source address */
#define XMT_BUFF_K_DATA		13				/* offset to start of packet data */

/*
 * Macro evaluates to "value" aligned to "size" bytes.  Make sure that
 * "size" is greater than 0 bytes.
 */

#define ALIGN(value,size) ((value + (size - 1)) & ~(size - 1))

/* Macro for checking a "value" is within a specific range */

#define IN_RANGE(value,low,high) ((value >= low) && (value <= high))

/* Only execute special print call when debug driver was built */

#ifdef DEFXX_DEBUG
#define DBG_printk(args...) printk(## args)
#else
#define DBG_printk(args...)
#endif

/* Define constants for masking/unmasking interrupts */

#define DFX_MASK_INTERRUPTS		1
#define DFX_UNMASK_INTERRUPTS	0

/* Define structure for driver transmit descriptor block */

typedef struct
	{
	struct sk_buff	*p_skb;					/* ptr to skb */
	} XMT_DRIVER_DESCR;

typedef struct DFX_board_tag
	{
	/* Keep virtual and physical pointers to locked, physically contiguous memory */

	PI_DESCR_BLOCK			*descr_block_virt;				/* PDQ descriptor block virt address */
	u32						descr_block_phys;				/* PDQ descriptor block phys address */
	PI_DMA_CMD_REQ			*cmd_req_virt;					/* Command request buffer virt address */
	u32						cmd_req_phys;					/* Command request buffer phys address */
	PI_DMA_CMD_RSP			*cmd_rsp_virt;					/* Command response buffer virt address */
	u32						cmd_rsp_phys;					/* Command response buffer phys address */
	char					*rcv_block_virt;				/* LLC host receive queue buf blk virt */
	u32						rcv_block_phys;					/* LLC host receive queue buf blk phys */
	PI_CONSUMER_BLOCK		*cons_block_virt;				/* PDQ consumer block virt address */
	u32						cons_block_phys;				/* PDQ consumer block phys address */

	/* Keep local copies of Type 1 and Type 2 register data */

	PI_TYPE_1_PROD_REG		cmd_req_reg;					/* Command Request register */
	PI_TYPE_1_PROD_REG		cmd_rsp_reg;					/* Command Response register */
	PI_TYPE_2_PROD_REG		rcv_xmt_reg;					/* Type 2 (RCV/XMT) register */

	/* Storage for unicast and multicast address entries in adapter CAM */

	u8						uc_table[1*FDDI_K_ALEN];
	u32						uc_count;						/* number of unicast addresses */
	u8						mc_table[PI_CMD_ADDR_FILTER_K_SIZE*FDDI_K_ALEN];
	u32						mc_count;						/* number of multicast addresses */

	/* Current packet filter settings */

	u32						ind_group_prom;					/* LLC individual & group frame prom mode */
	u32						group_prom;						/* LLC group (multicast) frame prom mode */

	/* Link available flag needed to determine whether to drop outgoing packet requests */

	u32						link_available;					/* is link available? */

	/* Resources to indicate reset type when resetting adapter */

	u32						reset_type;						/* skip or rerun diagnostics */

	/* Store pointers to receive buffers for queue processing code */

	char					*p_rcv_buff_va[PI_RCV_DATA_K_NUM_ENTRIES];

	/* Store pointers to transmit buffers for transmit completion code */

	XMT_DRIVER_DESCR		xmt_drv_descr_blk[PI_XMT_DATA_K_NUM_ENTRIES];
	
	/* Transmit spinlocks */
	
	spinlock_t			lock;

	/* Store device, bus-specific, and parameter information for this adapter */

	struct device			*dev;							/* pointer to device structure */
	u32						bus_type;						/* bus type (0 == PCI, 1 == EISA) */
	u16						base_addr;						/* base I/O address (same as dev->base_addr) */
	struct pci_dev *				pci_dev;
	u32						full_duplex_enb;				/* FDDI Full Duplex enable (1 == on, 2 == off) */
	u32						req_ttrt;						/* requested TTRT value (in 80ns units) */
	u32						burst_size;						/* adapter burst size (enumerated) */
	u32						rcv_bufs_to_post;				/* receive buffers to post for LLC host queue */
	u8						factory_mac_addr[FDDI_K_ALEN];	/* factory (on-board) MAC address */

	/* Common FDDI statistics structure and private counters */

	struct fddi_statistics	stats;

	u32						rcv_discards;
	u32						rcv_crc_errors;
	u32						rcv_frame_status_errors;
	u32						rcv_length_errors;
	u32						rcv_total_frames;
	u32						rcv_multicast_frames;
	u32						rcv_total_bytes;

	u32						xmt_discards;
	u32						xmt_length_errors;
	u32						xmt_total_frames;
	u32						xmt_total_bytes;
	} DFX_board_t;

#endif	/* #ifndef _DEFXX_H_ */