defxx.h

powerpc内核mpc8241linux系统下net驱动程序

	PI_CNTR		dup_addrs;
	PI_CNTR		dup_tokens;
	PI_CNTR		purge_errors;
	PI_CNTR		fci_strip_errors;
	PI_CNTR		traces_initiated;
	PI_CNTR		directed_beacons_rcvd;
	PI_CNTR		emac_frame_alignment_errors;
	PI_CNTR		ebuff_errors[PI_PHY_K_MAX];		/* Phy */
	PI_CNTR		lct_rejects[PI_PHY_K_MAX];
	PI_CNTR		lem_rejects[PI_PHY_K_MAX];
	PI_CNTR		link_errors[PI_PHY_K_MAX];
	PI_CNTR		connections[PI_PHY_K_MAX];
	PI_CNTR		copied_cnt;			 			/* Valid only if using SMT 7.3 */
	PI_CNTR		transmit_cnt;					/* Valid only if using SMT 7.3 */
	PI_CNTR		tokens;
	} PI_CNTR_BLK;

/* Counters_Get Request */

typedef struct
	{
	PI_UINT32  cmd_type;
	} PI_CMD_CNTRS_GET_REQ;

/* Counters_Get Response */

typedef struct
	{
	PI_RSP_HEADER   header;	
	PI_CNTR		time_since_reset;			
	PI_CNTR_BLK		cntrs;				
	} PI_CMD_CNTRS_GET_RSP;

/* Counters_Set Request */

typedef struct
	{
	PI_UINT32	cmd_type;
	PI_CNTR_BLK	cntrs;				
	} PI_CMD_CNTRS_SET_REQ;

/* Counters_Set Response */

typedef struct 
	{
	PI_RSP_HEADER   header;	
	} PI_CMD_CNTRS_SET_RSP;

/* Error_Log_Clear Request */

typedef struct
	{
	PI_UINT32  cmd_type;
	} PI_CMD_ERROR_LOG_CLEAR_REQ;

/* Error_Log_Clear Response */

typedef struct
	{
	PI_RSP_HEADER   header;	
	} PI_CMD_ERROR_LOG_CLEAR_RSP;

/* Error_Log_Get Request */

#define PI_LOG_ENTRY_K_INDEX_MIN	0		/* Minimum index for entry */

typedef struct
	{
	PI_UINT32  cmd_type;
	PI_UINT32  entry_index;
	} PI_CMD_ERROR_LOG_GET_REQ;

/* Error_Log_Get Response */

#define PI_K_LOG_FW_SIZE			111		/* Max number of fw longwords */
#define PI_K_LOG_DIAG_SIZE	 		6		/* Max number of diag longwords */

typedef struct
	{
	struct 
		{
		PI_UINT32	fru_imp_mask;
		PI_UINT32	test_id;
		PI_UINT32	reserved[PI_K_LOG_DIAG_SIZE];
		} diag;
	PI_UINT32		fw[PI_K_LOG_FW_SIZE];
	} PI_LOG_ENTRY;

typedef struct
	{
	PI_RSP_HEADER   header;	
	PI_UINT32		event_status;
	PI_UINT32		caller_id;
	PI_UINT32		timestamp_l;
	PI_UINT32		timestamp_h;
	PI_UINT32		write_count;
	PI_LOG_ENTRY	entry_info;
	} PI_CMD_ERROR_LOG_GET_RSP;

/* Define error log related constants and types.					*/
/*   Not all of the caller id's can occur.  The only ones currently */
/*   implemented are: none, selftest, mfg, fw, console				*/

#define PI_LOG_EVENT_STATUS_K_VALID		0	/* Valid Event Status 		*/
#define PI_LOG_EVENT_STATUS_K_INVALID	1	/* Invalid Event Status 	*/
#define PI_LOG_CALLER_ID_K_NONE		 	0	/* No caller 				*/
#define PI_LOG_CALLER_ID_K_SELFTEST	 	1	/* Normal power-up selftest */			
#define PI_LOG_CALLER_ID_K_MFG		 	2	/* Mfg power-up selftest 	*/
#define PI_LOG_CALLER_ID_K_ONLINE		3	/* On-line diagnostics 		*/
#define PI_LOG_CALLER_ID_K_HW			4	/* Hardware 				*/
#define PI_LOG_CALLER_ID_K_FW			5	/* Firmware 				*/
#define PI_LOG_CALLER_ID_K_CNS_HW		6	/* CNS firmware 			*/
#define PI_LOG_CALLER_ID_K_CNS_FW		7	/* CNS hardware 			*/
#define PI_LOG_CALLER_ID_K_CONSOLE	 	8   /* Console Caller Id 		*/

/*
 *  Place all DMA commands in the following request and response structures
 *  to simplify code.
 */

typedef union
	{
	PI_UINT32					cmd_type;
	PI_CMD_START_REQ			start;
	PI_CMD_FILTERS_SET_REQ		filter_set;
	PI_CMD_FILTERS_GET_REQ		filter_get;
	PI_CMD_CHARS_SET_REQ		char_set;
	PI_CMD_ADDR_FILTER_SET_REQ	addr_filter_set;
	PI_CMD_ADDR_FILTER_GET_REQ	addr_filter_get;
	PI_CMD_STATUS_CHARS_GET_REQ	stat_char_get;
	PI_CMD_CNTRS_GET_REQ		cntrs_get;
	PI_CMD_CNTRS_SET_REQ		cntrs_set;
	PI_CMD_ERROR_LOG_CLEAR_REQ	error_log_clear;
	PI_CMD_ERROR_LOG_GET_REQ	error_log_read;
	PI_CMD_SNMP_SET_REQ			snmp_set;
	PI_CMD_FDDI_MIB_GET_REQ		fddi_mib_get;
	PI_CMD_DEC_EXT_MIB_GET_REQ	dec_mib_get;
	PI_CMD_SMT_MIB_SET_REQ		smt_mib_set;
	PI_CMD_SMT_MIB_GET_REQ		smt_mib_get;
	char						pad[PI_CMD_REQ_K_SIZE_MAX]; 
	} PI_DMA_CMD_REQ;

typedef union
	{
	PI_RSP_HEADER				header;
	PI_CMD_START_RSP			start;
	PI_CMD_FILTERS_SET_RSP		filter_set;
	PI_CMD_FILTERS_GET_RSP		filter_get;
	PI_CMD_CHARS_SET_RSP		char_set;
	PI_CMD_ADDR_FILTER_SET_RSP	addr_filter_set;
	PI_CMD_ADDR_FILTER_GET_RSP	addr_filter_get;
	PI_CMD_STATUS_CHARS_GET_RSP	stat_char_get;
	PI_CMD_CNTRS_GET_RSP		cntrs_get;
	PI_CMD_CNTRS_SET_RSP		cntrs_set;
	PI_CMD_ERROR_LOG_CLEAR_RSP	error_log_clear;
	PI_CMD_ERROR_LOG_GET_RSP	error_log_get;
	PI_CMD_SNMP_SET_RSP			snmp_set;
	PI_CMD_FDDI_MIB_GET_RSP		fddi_mib_get;
	PI_CMD_DEC_EXT_MIB_GET_RSP	dec_mib_get;
	PI_CMD_SMT_MIB_SET_RSP		smt_mib_set;
	PI_CMD_SMT_MIB_GET_RSP		smt_mib_get;
	char						pad[PI_CMD_RSP_K_SIZE_MAX]; 
	} PI_DMA_CMD_RSP;

typedef union
	{
	PI_DMA_CMD_REQ	request;
	PI_DMA_CMD_RSP	response;
	} PI_DMA_CMD_BUFFER;


/* Define format of Consumer Block (resident in host memory) */

typedef struct
	{
	volatile PI_UINT32	xmt_rcv_data;
	volatile PI_UINT32	reserved_1;
	volatile PI_UINT32	smt_host;
	volatile PI_UINT32	reserved_2;
	volatile PI_UINT32	unsol;
	volatile PI_UINT32	reserved_3;
	volatile PI_UINT32	cmd_rsp;
	volatile PI_UINT32	reserved_4;
	volatile PI_UINT32	cmd_req;
	volatile PI_UINT32	reserved_5;
	} PI_CONSUMER_BLOCK;

#define PI_CONS_M_RCV_INDEX			0x000000FF
#define PI_CONS_M_XMT_INDEX			0x00FF0000
#define PI_CONS_V_RCV_INDEX			0
#define PI_CONS_V_XMT_INDEX			16

/* Offsets into consumer block */

#define PI_CONS_BLK_K_XMT_RCV		0x00
#define PI_CONS_BLK_K_SMT_HOST		0x08
#define PI_CONS_BLK_K_UNSOL			0x10
#define PI_CONS_BLK_K_CMD_RSP		0x18
#define PI_CONS_BLK_K_CMD_REQ		0x20

/* Offsets into descriptor block */

#define PI_DESCR_BLK_K_RCV_DATA		0x0000
#define PI_DESCR_BLK_K_XMT_DATA		0x0800
#define PI_DESCR_BLK_K_SMT_HOST 	0x1000
#define PI_DESCR_BLK_K_UNSOL		0x1200
#define PI_DESCR_BLK_K_CMD_RSP		0x1280
#define PI_DESCR_BLK_K_CMD_REQ		0x1300	

/* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host)   */
/*   Note a field has been added for later versions of the PDQ to allow for  */
/*   finer granularity of the rcv buffer alignment.  For backwards		 	 */
/*   compatibility, the two bits (which allow the rcv buffer to be longword  */
/*   aligned) have been added at the MBZ bits.  To support previous drivers, */
/*   the MBZ definition is left intact.									  	 */

typedef struct
	{
	PI_UINT32	long_0;
	PI_UINT32	long_1;
	} PI_RCV_DESCR;

#define	PI_RCV_DESCR_M_SOP	  		0x80000000
#define PI_RCV_DESCR_M_SEG_LEN_LO 	0x60000000 
#define PI_RCV_DESCR_M_MBZ	  		0x60000000 
#define PI_RCV_DESCR_M_SEG_LEN		0x1F800000
#define PI_RCV_DESCR_M_SEG_LEN_HI	0x1FF00000	  
#define PI_RCV_DESCR_M_SEG_CNT	  	0x000F0000
#define PI_RCV_DESCR_M_BUFF_HI	  	0x0000FFFF

#define	PI_RCV_DESCR_V_SOP	  		31
#define PI_RCV_DESCR_V_SEG_LEN_LO 	29
#define PI_RCV_DESCR_V_MBZ	  		29
#define PI_RCV_DESCR_V_SEG_LEN	  	23
#define PI_RCV_DESCR_V_SEG_LEN_HI 	20	  
#define PI_RCV_DESCR_V_SEG_CNT	  	16
#define PI_RCV_DESCR_V_BUFF_HI	 	0

/* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */

typedef struct
	{
	PI_UINT32	long_0;
	PI_UINT32	long_1;
	} PI_XMT_DESCR;

#define	PI_XMT_DESCR_M_SOP			0x80000000
#define PI_XMT_DESCR_M_EOP			0x40000000
#define PI_XMT_DESCR_M_MBZ			0x20000000 
#define PI_XMT_DESCR_M_SEG_LEN		0x1FFF0000
#define PI_XMT_DESCR_M_BUFF_HI		0x0000FFFF

#define	PI_XMT_DESCR_V_SOP			31
#define	PI_XMT_DESCR_V_EOP			30
#define PI_XMT_DESCR_V_MBZ			29
#define PI_XMT_DESCR_V_SEG_LEN		16
#define PI_XMT_DESCR_V_BUFF_HI		0

/* Define format of the Descriptor Block (resident in host memory) */

#define PI_RCV_DATA_K_NUM_ENTRIES			256
#define PI_XMT_DATA_K_NUM_ENTRIES			256
#define PI_SMT_HOST_K_NUM_ENTRIES			64
#define PI_UNSOL_K_NUM_ENTRIES				16
#define PI_CMD_RSP_K_NUM_ENTRIES			16
#define PI_CMD_REQ_K_NUM_ENTRIES			16

typedef struct
	{
	PI_RCV_DESCR  rcv_data[PI_RCV_DATA_K_NUM_ENTRIES];
	PI_XMT_DESCR  xmt_data[PI_XMT_DATA_K_NUM_ENTRIES];
	PI_RCV_DESCR  smt_host[PI_SMT_HOST_K_NUM_ENTRIES];
	PI_RCV_DESCR  unsol[PI_UNSOL_K_NUM_ENTRIES];
	PI_RCV_DESCR  cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES];
	PI_XMT_DESCR  cmd_req[PI_CMD_REQ_K_NUM_ENTRIES];
	} PI_DESCR_BLOCK;

/* Define Port Registers - offsets from PDQ Base address */

#define PI_PDQ_K_REG_PORT_RESET			0x00000000
#define PI_PDQ_K_REG_HOST_DATA			0x00000004
#define PI_PDQ_K_REG_PORT_CTRL			0x00000008
#define PI_PDQ_K_REG_PORT_DATA_A		0x0000000C
#define PI_PDQ_K_REG_PORT_DATA_B		0x00000010
#define PI_PDQ_K_REG_PORT_STATUS		0x00000014
#define PI_PDQ_K_REG_TYPE_0_STATUS 		0x00000018
#define PI_PDQ_K_REG_HOST_INT_ENB	  	0x0000001C
#define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 	0x00000020
#define PI_PDQ_K_REG_TYPE_2_PROD		0x00000024
#define PI_PDQ_K_REG_CMD_RSP_PROD		0x00000028
#define PI_PDQ_K_REG_CMD_REQ_PROD		0x0000002C
#define PI_PDQ_K_REG_SMT_HOST_PROD   	0x00000030
#define PI_PDQ_K_REG_UNSOL_PROD			0x00000034

/* Port Control Register - Command codes for primary commands */

#define PI_PCTRL_M_CMD_ERROR			0x8000
#define PI_PCTRL_M_BLAST_FLASH			0x4000
#define PI_PCTRL_M_HALT					0x2000
#define PI_PCTRL_M_COPY_DATA			0x1000
#define PI_PCTRL_M_ERROR_LOG_START		0x0800
#define PI_PCTRL_M_ERROR_LOG_READ		0x0400
#define PI_PCTRL_M_XMT_DATA_FLUSH_DONE	0x0200
#define PI_PCTRL_M_INIT					0x0100
#define PI_PCTRL_M_INIT_START		    0x0080
#define PI_PCTRL_M_CONS_BLOCK			0x0040
#define PI_PCTRL_M_UNINIT				0x0020
#define PI_PCTRL_M_RING_MEMBER			0x0010
#define PI_PCTRL_M_MLA					0x0008		
#define PI_PCTRL_M_FW_REV_READ			0x0004
#define PI_PCTRL_M_DEV_SPECIFIC			0x0002
#define PI_PCTRL_M_SUB_CMD				0x0001

/* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */

#define PI_SUB_CMD_K_LINK_UNINIT		0x0001
#define PI_SUB_CMD_K_BURST_SIZE_SET		0x0002
#define PI_SUB_CMD_K_PDQ_REV_GET		0x0004
#define PI_SUB_CMD_K_HW_REV_GET			0x0008

/* Define some Port Data B values */

#define PI_PDATA_B_DMA_BURST_SIZE_4	 	0		/* valid values for command */
#define PI_PDATA_B_DMA_BURST_SIZE_8	 	1
#define PI_PDATA_B_DMA_BURST_SIZE_16	2
#define PI_PDATA_B_DMA_BURST_SIZE_32	3		/* not supported on PCI */
#define PI_PDATA_B_DMA_BURST_SIZE_DEF	PI_PDATA_B_DMA_BURST_SIZE_16

/* Port Data A Reset state */

#define PI_PDATA_A_RESET_M_UPGRADE		0x00000001
#define PI_PDATA_A_RESET_M_SOFT_RESET	0x00000002
#define PI_PDATA_A_RESET_M_SKIP_ST		0x00000004

/* Read adapter MLA address port control command constants */

#define PI_PDATA_A_MLA_K_LO				0
#define PI_PDATA_A_MLA_K_HI				1

/* Byte Swap values for init command */

#define PI_PDATA_A_INIT_M_DESC_BLK_ADDR			0x0FFFFE000
#define PI_PDATA_A_INIT_M_RESERVED				0x000001FFC
#define PI_PDATA_A_INIT_M_BSWAP_DATA			0x000000002 
#define PI_PDATA_A_INIT_M_BSWAP_LITERAL			0x000000001

#define PI_PDATA_A_INIT_V_DESC_BLK_ADDR			13
#define PI_PDATA_A_INIT_V_RESERVED				3
#define PI_PDATA_A_INIT_V_BSWAP_DATA			1 
#define PI_PDATA_A_INIT_V_BSWAP_LITERAL			0

/* Port Reset Register */

#define PI_RESET_M_ASSERT_RESET			1

/* Port Status register */

#define PI_PSTATUS_V_RCV_DATA_PENDING	31
#define PI_PSTATUS_V_XMT_DATA_PENDING	30
#define PI_PSTATUS_V_SMT_HOST_PENDING	29
#define PI_PSTATUS_V_UNSOL_PENDING		28
#define PI_PSTATUS_V_CMD_RSP_PENDING	27
#define PI_PSTATUS_V_CMD_REQ_PENDING	26
#define PI_PSTATUS_V_TYPE_0_PENDING		25
#define PI_PSTATUS_V_RESERVED_1			16
#define PI_PSTATUS_V_RESERVED_2			11
#define PI_PSTATUS_V_STATE				8
#define PI_PSTATUS_V_HALT_ID			0

#define PI_PSTATUS_M_RCV_DATA_PENDING	0x80000000
#define PI_PSTATUS_M_XMT_DATA_PENDING	0x40000000
#define PI_PSTATUS_M_SMT_HOST_PENDING	0x20000000
#define PI_PSTATUS_M_UNSOL_PENDING		0x10000000
#define PI_PSTATUS_M_CMD_RSP_PENDING	0x08000000
#define PI_PSTATUS_M_CMD_REQ_PENDING	0x04000000
#define PI_PSTATUS_M_TYPE_0_PENDING		0x02000000
#define PI_PSTATUS_M_RESERVED_1			0x01FF0000
#define PI_PSTATUS_M_RESERVED_2			0x0000F800
#define PI_PSTATUS_M_STATE				0x00000700
#define PI_PSTATUS_M_HALT_ID			0x000000FF

/* Define Halt Id's			 					*/
/*   Do not insert into this list, only append. */

#define PI_HALT_ID_K_SELFTEST_TIMEOUT	0
#define PI_HALT_ID_K_PARITY_ERROR		1
#define PI_HALT_ID_K_HOST_DIR_HALT		2
#define PI_HALT_ID_K_SW_FAULT			3
#define PI_HALT_ID_K_HW_FAULT			4
#define PI_HALT_ID_K_PC_TRACE			5
#define PI_HALT_ID_K_DMA_ERROR			6			/* Host Data has error reg */
#define PI_HALT_ID_K_IMAGE_CRC_ERROR	7   		/* Image is bad, update it */
#define PI_HALT_ID_K_BUS_EXCEPTION	 	8   		/* 68K bus exception	   */

/* Host Interrupt Enable Register as seen by host */ 

#define PI_HOST_INT_M_XMT_DATA_ENB		0x80000000	/* Type 2 Enables */
#define PI_HOST_INT_M_RCV_DATA_ENB		0x40000000  
#define PI_HOST_INT_M_SMT_HOST_ENB		0x10000000	/* Type 1 Enables */ 
#define PI_HOST_INT_M_UNSOL_ENB			0x20000000
#define PI_HOST_INT_M_CMD_RSP_ENB		0x08000000
#define PI_HOST_INT_M_CMD_REQ_ENB		0x04000000
#define	PI_HOST_INT_M_TYPE_1_RESERVED	0x00FF0000
#define	PI_HOST_INT_M_TYPE_0_RESERVED	0x0000FF00	/* Type 0 Enables */
#define PI_HOST_INT_M_1MS				0x00000080
#define PI_HOST_INT_M_20MS				0x00000040
#define PI_HOST_INT_M_CSR_CMD_DONE		0x00000020
#define PI_HOST_INT_M_STATE_CHANGE		0x00000010
#define PI_HOST_INT_M_XMT_FLUSH			0x00000008
#define PI_HOST_INT_M_NXM				0x00000004
#define PI_HOST_INT_M_PM_PAR_ERR		0x00000002
#define PI_HOST_INT_M_BUS_PAR_ERR		0x00000001

#define PI_HOST_INT_V_XMT_DATA_ENB		31			/* Type 2 Enables */
#define PI_HOST_INT_V_RCV_DATA_ENB		30  
#define PI_HOST_INT_V_SMT_HOST_ENB		29			/* Type 1 Enables */ 
#define PI_HOST_INT_V_UNSOL_ENB			28
#define PI_HOST_INT_V_CMD_RSP_ENB		27
#define PI_HOST_INT_V_CMD_REQ_ENB		26
#define	PI_HOST_INT_V_TYPE_1_RESERVED	16
#define	PI_HOST_INT_V_TYPE_0_RESERVED   8			/* Type 0 Enables */
#define PI_HOST_INT_V_1MS_ENB			7
#define PI_HOST_INT_V_20MS_ENB			6
#define PI_HOST_INT_V_CSR_CMD_DONE_ENB	5
#define PI_HOST_INT_V_STATE_CHANGE_ENB	4
#define PI_HOST_INT_V_XMT_FLUSH_ENB 	3
#define PI_HOST_INT_V_NXM_ENB			2
#define PI_HOST_INT_V_PM_PAR_ERR_ENB	1
#define PI_HOST_INT_V_BUS_PAR_ERR_ENB	0

#define PI_HOST_INT_K_ACK_ALL_TYPE_0	0x000000FF
#define PI_HOST_INT_K_DISABLE_ALL_INTS	0x00000000
#define PI_HOST_INT_K_ENABLE_ALL_INTS	0xFFFFFFFF
#define PI_HOST_INT_K_ENABLE_DEF_INTS	0xC000001F

/* Type 0 Interrupt Status Register */

#define PI_TYPE_0_STAT_M_1MS			0x00000080
#define PI_TYPE_0_STAT_M_20MS			0x00000040
#define PI_TYPE_0_STAT_M_CSR_CMD_DONE	0x00000020
#define PI_TYPE_0_STAT_M_STATE_CHANGE	0x00000010
#define PI_TYPE_0_STAT_M_XMT_FLUSH		0x00000008
#define PI_TYPE_0_STAT_M_NXM			0x00000004
#define PI_TYPE_0_STAT_M_PM_PAR_ERR		0x00000002
#define PI_TYPE_0_STAT_M_BUS_PAR_ERR	0x00000001

#define PI_TYPE_0_STAT_V_1MS			7