jtag.tan.rpt

Altera USB制作材料！有usb驱动！FPGA码源

; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK12MHz        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK12MHz'                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                          ; To                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 138.54 MHz ( period = 7.218 ns )                    ; jtag_logic:inst6|state[3]     ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.509 ns                ;
; N/A                                     ; 138.97 MHz ( period = 7.196 ns )                    ; jtag_logic:inst6|bitcount[1]  ; jtag_logic:inst6|state[3]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.487 ns                ;
; N/A                                     ; 139.96 MHz ( period = 7.145 ns )                    ; jtag_logic:inst6|bitcount[2]  ; jtag_logic:inst6|state[3]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.436 ns                ;
; N/A                                     ; 142.21 MHz ( period = 7.032 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.323 ns                ;
; N/A                                     ; 143.84 MHz ( period = 6.952 ns )                    ; jtag_logic:inst6|bitcount[4]  ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.243 ns                ;
; N/A                                     ; 144.99 MHz ( period = 6.897 ns )                    ; jtag_logic:inst6|state[3]     ; jtag_logic:inst6|state[1]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.188 ns                ;
; N/A                                     ; 145.48 MHz ( period = 6.874 ns )                    ; jtag_logic:inst6|bitcount[0]  ; jtag_logic:inst6|state[3]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.165 ns                ;
; N/A                                     ; 146.26 MHz ( period = 6.837 ns )                    ; jtag_logic:inst6|bitcount[1]  ; jtag_logic:inst6|state[1]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.128 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|B_TDI        ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.088 ns                ;
; N/A                                     ; 147.36 MHz ( period = 6.786 ns )                    ; jtag_logic:inst6|bitcount[2]  ; jtag_logic:inst6|state[1]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 6.077 ns                ;
; N/A                                     ; 149.08 MHz ( period = 6.708 ns )                    ; jtag_logic:inst6|state[2]     ; jtag_logic:inst6|state[1]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.999 ns                ;
; N/A                                     ; 149.23 MHz ( period = 6.701 ns )                    ; jtag_logic:inst6|bitcount[7]  ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.992 ns                ;
; N/A                                     ; 149.54 MHz ( period = 6.687 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|ioshifter[0] ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 149.77 MHz ( period = 6.677 ns )                    ; jtag_logic:inst6|bitcount[6]  ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.968 ns                ;
; N/A                                     ; 149.95 MHz ( period = 6.669 ns )                    ; jtag_logic:inst6|bitcount[5]  ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.960 ns                ;
; N/A                                     ; 150.02 MHz ( period = 6.666 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|bitcount[0]  ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.957 ns                ;
; N/A                                     ; 150.02 MHz ( period = 6.666 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|bitcount[1]  ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.957 ns                ;
; N/A                                     ; 150.02 MHz ( period = 6.666 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|bitcount[2]  ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.957 ns                ;
; N/A                                     ; 150.02 MHz ( period = 6.666 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|bitcount[3]  ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.957 ns                ;
; N/A                                     ; 150.02 MHz ( period = 6.666 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|bitcount[4]  ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.957 ns                ;
; N/A                                     ; 150.02 MHz ( period = 6.666 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|bitcount[5]  ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.957 ns                ;
; N/A                                     ; 150.02 MHz ( period = 6.666 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|bitcount[6]  ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.957 ns                ;
; N/A                                     ; 150.02 MHz ( period = 6.666 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|bitcount[7]  ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.957 ns                ;
; N/A                                     ; 150.02 MHz ( period = 6.666 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|bitcount[8]  ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.957 ns                ;
; N/A                                     ; 150.65 MHz ( period = 6.638 ns )                    ; jtag_logic:inst6|state[3]     ; jtag_logic:inst6|ioshifter[5] ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.929 ns                ;
; N/A                                     ; 150.74 MHz ( period = 6.634 ns )                    ; jtag_logic:inst6|state[1]     ; jtag_logic:inst6|ioshifter[6] ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.925 ns                ;
; N/A                                     ; 150.88 MHz ( period = 6.628 ns )                    ; jtag_logic:inst6|do_output    ; jtag_logic:inst6|state[1]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.919 ns                ;
; N/A                                     ; 150.99 MHz ( period = 6.623 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|B_TMS        ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.914 ns                ;
; N/A                                     ; 150.99 MHz ( period = 6.623 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|B_NCS        ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.914 ns                ;
; N/A                                     ; 152.11 MHz ( period = 6.574 ns )                    ; jtag_logic:inst6|bitcount[1]  ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.865 ns                ;
; N/A                                     ; 152.56 MHz ( period = 6.555 ns )                    ; jtag_logic:inst6|state[3]     ; jtag_logic:inst6|B_TDI        ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.846 ns                ;
; N/A                                     ; 152.81 MHz ( period = 6.544 ns )                    ; jtag_logic:inst6|state[2]     ; jtag_logic:inst6|ioshifter[5] ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.835 ns                ;
; N/A                                     ; 153.16 MHz ( period = 6.529 ns )                    ; jtag_logic:inst6|state[0]     ; jtag_logic:inst6|carry        ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.820 ns                ;
; N/A                                     ; 153.30 MHz ( period = 6.523 ns )                    ; jtag_logic:inst6|bitcount[2]  ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.814 ns                ;
; N/A                                     ; 153.40 MHz ( period = 6.519 ns )                    ; jtag_logic:inst6|bitcount[3]  ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.810 ns                ;
; N/A                                     ; 153.49 MHz ( period = 6.515 ns )                    ; jtag_logic:inst6|bitcount[0]  ; jtag_logic:inst6|state[1]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.806 ns                ;
; N/A                                     ; 153.87 MHz ( period = 6.499 ns )                    ; jtag_logic:inst6|state[2]     ; jtag_logic:inst6|B_TDI        ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.790 ns                ;
; N/A                                     ; 154.23 MHz ( period = 6.484 ns )                    ; jtag_logic:inst6|state[3]     ; jtag_logic:inst6|ioshifter[0] ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.775 ns                ;
; N/A                                     ; 154.25 MHz ( period = 6.483 ns )                    ; jtag_logic:inst6|ioshifter[6] ; jtag_logic:inst6|state[0]     ; CLK12MHz   ; CLK12MHz ; None                        ; None                      ; 5.774 ns                ;