traffic_fsm.v

此代码为多路交通灯控制

module traffic_fsm (clk, 
                    rst, 
                    red1,
                    yellow1, 
                    green1, 
                    red2, 
                    yellow2, 
                    green2);

    input clk, rst;
    output red1, yellow1, green1, red2, yellow2, green2;
    reg red1, yellow1, green1, red2, yellow2, green2;
    reg [2:0] currentstate, nextstate ;
    reg [8:0] counter1;//counter2;
    reg flag1;//60s
    //reg flag2;//30s
    
    parameter s0 = 3'b000; parameter s1 = 3'b001;
    parameter s2 = 3'b010; parameter s3 = 3'b011;
    
  always @(posedge clk or negedge rst)
       begin
         if (!rst) 
            currentstate<=s0 ;
         else if(flag1)
            currentstate<=nextstate;
      end

  always @(currentstate)
    begin
          red1=1'b0; 
          yellow1=1'b0; 
          green1=1'b0;
          red2=1'b0; 
          yellow2=1'b0; 
          green2=1'b0;//cross - two directions
          
        case (currentstate) 
            s0:
             //if(flag1)
             begin
                green1=1'b1;
                red2=1'b1;
                nextstate=s1;
              end
              //else nextstate=s3;
          s1: 
          //if(flag2)
           begin 
              yellow1=1'b1;
              yellow2=1'b1;
              nextstate=s2;
            end
           // else nextstate=s0;
           
         s2:
        // if(flag1)
         begin 
             red1=1'b1;
             green2=1'b1;
             nextstate=s3;
           end
          // else nextstate=s1;
           
         s3:
        // if(flag2)
         begin
            yellow1 =1'b1;          
            yellow2 =1'b1;
            nextstate =s0;
           end   
           //else nextstate=s2;  
           endcase
     end  
   always @(posedge clk or negedge rst)//counter model
       if(!rst)
       begin
        counter1<=0;
        flag1<=0;
        end
        else if(counter1==7)
        counter1<=0;
       else case(counter1)
       2:begin
       counter1<=counter1+1;
       flag1<=1;
       end
       5:begin
       counter1<=counter1+1;
       flag1<=1;
       end
       default:begin
       flag1<=0;
       counter1<=counter1+1;
   end
       endcase
       
   //begin
    //   flag1<=1;
     //  counter1<=0;
  // end
      
 // else
    //   begin
     //   counter1<=counter1+1;
     //   flag1<=0;
  // end
    //always @(posedge clk or negedge rst)
    // if(!rst)
   //  begin
     //   counter2<=0;
       //  flag2<=0;
     // end
      // else if(counter2==3)
  // begin
    //   flag2<=1;
    //   counter2<=0;
  // end
  // else
   //   begin
   //      counter2<=counter2+1;
   //     flag2<=0;
   //   end
endmodule