📄 lcdcont.tan.qmsg

📁 关于lcd的vhdl程序代码
💻 QMSG
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{ "Info" "ITDB_FULL_TCO_RESULT" "clk data_out\[0\] lcd:mylcd\|lcd_data\[0\] 11.283 ns register " "Info: tco from clock \"clk\" to destination pin \"data_out\[0\]\" through register \"lcd:mylcd\|lcd_data\[0\]\" is 11.283 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.766 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.321 ns) 4.222 ns clockdiv:div\|clockout 2 REG LC_X12_Y3_N9 21 " "Info: 2: + IC(1.738 ns) + CELL(1.321 ns) = 4.222 ns; Loc. = LC_X12_Y3_N9; Fanout = 21; REG Node = 'clockdiv:div\|clockout'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.059 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.607 ns) + CELL(0.937 ns) 7.766 ns lcd:mylcd\|lcd_data\[0\] 3 REG LC_X16_Y5_N2 1 " "Info: 3: + IC(2.607 ns) + CELL(0.937 ns) = 7.766 ns; Loc. = LC_X16_Y5_N2; Fanout = 1; REG Node = 'lcd:mylcd\|lcd_data\[0\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.544 ns" { clockdiv:div|clockout lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.421 ns 44.05 % " "Info: Total cell delay = 3.421 ns ( 44.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.345 ns 55.95 % " "Info: Total interconnect delay = 4.345 ns ( 55.95 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lcd_data[0] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.384 ns + " "Info: + Micro clock to output delay of source is 0.384 ns" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.133 ns + Longest register pin " "Info: + Longest register to pin delay is 3.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:mylcd\|lcd_data\[0\] 1 REG LC_X16_Y5_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y5_N2; Fanout = 1; REG Node = 'lcd:mylcd\|lcd_data\[0\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(2.322 ns) 3.133 ns data_out\[0\] 2 PIN PIN_91 0 " "Info: 2: + IC(0.811 ns) + CELL(2.322 ns) = 3.133 ns; Loc. = PIN_91; Fanout = 0; PIN Node = 'data_out\[0\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.133 ns" { lcd:mylcd|lcd_data[0] data_out[0] } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 74.11 % " "Info: Total cell delay = 2.322 ns ( 74.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.811 ns 25.89 % " "Info: Total interconnect delay = 0.811 ns ( 25.89 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.133 ns" { lcd:mylcd|lcd_data[0] data_out[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "3.133 ns" { lcd:mylcd|lcd_data[0] data_out[0] } { 0.000ns 0.811ns } { 0.000ns 2.322ns } } }  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lcd_data[0] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.133 ns" { lcd:mylcd|lcd_data[0] data_out[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "3.133 ns" { lcd:mylcd|lcd_data[0] data_out[0] } { 0.000ns 0.811ns } { 0.000ns 2.322ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lcd:mylcd\|lcd_data\[6\] reset clk 1.176 ns register " "Info: th for register \"lcd:mylcd\|lcd_data\[6\]\" (data pin = \"reset\", clock pin = \"clk\") is 1.176 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.766 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.321 ns) 4.222 ns clockdiv:div\|clockout 2 REG LC_X12_Y3_N9 21 " "Info: 2: + IC(1.738 ns) + CELL(1.321 ns) = 4.222 ns; Loc. = LC_X12_Y3_N9; Fanout = 21; REG Node = 'clockdiv:div\|clockout'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.059 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.607 ns) + CELL(0.937 ns) 7.766 ns lcd:mylcd\|lcd_data\[6\] 3 REG LC_X16_Y6_N2 1 " "Info: 3: + IC(2.607 ns) + CELL(0.937 ns) = 7.766 ns; Loc. = LC_X16_Y6_N2; Fanout = 1; REG Node = 'lcd:mylcd\|lcd_data\[6\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.544 ns" { clockdiv:div|clockout lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.421 ns 44.05 % " "Info: Total cell delay = 3.421 ns ( 44.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.345 ns 55.95 % " "Info: Total interconnect delay = 4.345 ns ( 55.95 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lcd_data[6] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.225 ns + " "Info: + Micro hold delay of destination is 0.225 ns" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.815 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_38 19 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_38; Fanout = 19; PIN Node = 'reset'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { reset } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.415 ns) + CELL(1.268 ns) 6.815 ns lcd:mylcd\|lcd_data\[6\] 2 REG LC_X16_Y6_N2 1 " "Info: 2: + IC(4.415 ns) + CELL(1.268 ns) = 6.815 ns; Loc. = LC_X16_Y6_N2; Fanout = 1; REG Node = 'lcd:mylcd\|lcd_data\[6\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "5.683 ns" { reset lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns 35.22 % " "Info: Total cell delay = 2.400 ns ( 35.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.415 ns 64.78 % " "Info: Total interconnect delay = 4.415 ns ( 64.78 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "6.815 ns" { reset lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "6.815 ns" { reset reset~combout lcd:mylcd|lcd_data[6] } { 0.000ns 0.000ns 4.415ns } { 0.000ns 1.132ns 1.268ns } } }  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lcd_data[6] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "6.815 ns" { reset lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "6.815 ns" { reset reset~combout lcd:mylcd|lcd_data[6] } { 0.000ns 0.000ns 4.415ns } { 0.000ns 1.132ns 1.268ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 26 16:49:22 2005 " "Info: Processing ended: Wed Oct 26 16:49:22 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
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