lcdcont.tan.qmsg

关于lcd的vhdl程序代码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 9 -1 0 } } { "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clockdiv:div\|clockout " "Info: Detected ripple clock \"clockdiv:div\|clockout\" as buffer" {  } { { "clockdiv.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/clockdiv.vhd" 10 -1 0 } } { "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" 1 { { 0 "clockdiv:div\|clockout" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[2\] register lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[0\] 121.79 MHz 8.211 ns Internal " "Info: Clock \"clk\" has Internal fmax of 121.79 MHz between source register \"lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[2\]\" and destination register \"lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[0\]\" (period= 8.211 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.647 ns + Longest register register " "Info: + Longest register to register delay is 7.647 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[2\] 1 REG LC_X15_Y5_N3 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y5_N3; Fanout = 13; REG Node = 'lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[2\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_p78.tdf" "" { Text "F:/quartus/演示程序/lcd_zifu/db/cntr_p78.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.160 ns) + CELL(0.755 ns) 2.915 ns lcd:mylcd\|count\[3\]~439 2 COMB LC_X15_Y6_N4 3 " "Info: 2: + IC(2.160 ns) + CELL(0.755 ns) = 2.915 ns; Loc. = LC_X15_Y6_N4; Fanout = 3; COMB Node = 'lcd:mylcd\|count\[3\]~439'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "2.915 ns" { lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] lcd:mylcd|count[3]~439 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.204 ns) 3.664 ns lcd:mylcd\|count\[3\]~440 3 COMB LC_X15_Y6_N5 1 " "Info: 3: + IC(0.545 ns) + CELL(0.204 ns) = 3.664 ns; Loc. = LC_X15_Y6_N5; Fanout = 1; COMB Node = 'lcd:mylcd\|count\[3\]~440'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "0.749 ns" { lcd:mylcd|count[3]~439 lcd:mylcd|count[3]~440 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.811 ns) + CELL(0.204 ns) 5.679 ns lcd:mylcd\|count\[3\]~442 4 COMB LC_X15_Y5_N0 4 " "Info: 4: + IC(1.811 ns) + CELL(0.204 ns) = 5.679 ns; Loc. = LC_X15_Y5_N0; Fanout = 4; COMB Node = 'lcd:mylcd\|count\[3\]~442'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "2.015 ns" { lcd:mylcd|count[3]~440 lcd:mylcd|count[3]~442 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.268 ns) 7.647 ns lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[0\] 5 REG LC_X15_Y5_N1 16 " "Info: 5: + IC(0.700 ns) + CELL(1.268 ns) = 7.647 ns; Loc. = LC_X15_Y5_N1; Fanout = 16; REG Node = 'lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[0\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "1.968 ns" { lcd:mylcd|count[3]~442 lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_p78.tdf" "" { Text "F:/quartus/演示程序/lcd_zifu/db/cntr_p78.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.431 ns 31.79 % " "Info: Total cell delay = 2.431 ns ( 31.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.216 ns 68.21 % " "Info: Total interconnect delay = 5.216 ns ( 68.21 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.647 ns" { lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] lcd:mylcd|count[3]~439 lcd:mylcd|count[3]~440 lcd:mylcd|count[3]~442 lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.647 ns" { lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] lcd:mylcd|count[3]~439 lcd:mylcd|count[3]~440 lcd:mylcd|count[3]~442 lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } { 0.000ns 2.160ns 0.545ns 1.811ns 0.700ns } { 0.000ns 0.755ns 0.204ns 0.204ns 1.268ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.766 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.321 ns) 4.222 ns clockdiv:div\|clockout 2 REG LC_X12_Y3_N9 21 " "Info: 2: + IC(1.738 ns) + CELL(1.321 ns) = 4.222 ns; Loc. = LC_X12_Y3_N9; Fanout = 21; REG Node = 'clockdiv:div\|clockout'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.059 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.607 ns) + CELL(0.937 ns) 7.766 ns lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[0\] 3 REG LC_X15_Y5_N1 16 " "Info: 3: + IC(2.607 ns) + CELL(0.937 ns) = 7.766 ns; Loc. = LC_X15_Y5_N1; Fanout = 16; REG Node = 'lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[0\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.544 ns" { clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_p78.tdf" "" { Text "F:/quartus/演示程序/lcd_zifu/db/cntr_p78.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.421 ns 44.05 % " "Info: Total cell delay = 3.421 ns ( 44.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.345 ns 55.95 % " "Info: Total interconnect delay = 4.345 ns ( 55.95 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.766 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.321 ns) 4.222 ns clockdiv:div\|clockout 2 REG LC_X12_Y3_N9 21 " "Info: 2: + IC(1.738 ns) + CELL(1.321 ns) = 4.222 ns; Loc. = LC_X12_Y3_N9; Fanout = 21; REG Node = 'clockdiv:div\|clockout'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.059 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.607 ns) + CELL(0.937 ns) 7.766 ns lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[2\] 3 REG LC_X15_Y5_N3 13 " "Info: 3: + IC(2.607 ns) + CELL(0.937 ns) = 7.766 ns; Loc. = LC_X15_Y5_N3; Fanout = 13; REG Node = 'lcd:mylcd\|lpm_counter:count_rtl_0\|cntr_p78:auto_generated\|safe_q\[2\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.544 ns" { clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_p78.tdf" "" { Text "F:/quartus/演示程序/lcd_zifu/db/cntr_p78.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.421 ns 44.05 % " "Info: Total cell delay = 3.421 ns ( 44.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.345 ns 55.95 % " "Info: Total interconnect delay = 4.345 ns ( 55.95 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.384 ns + " "Info: + Micro clock to output delay of source is 0.384 ns" {  } { { "db/cntr_p78.tdf" "" { Text "F:/quartus/演示程序/lcd_zifu/db/cntr_p78.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.180 ns + " "Info: + Micro setup delay of destination is 0.180 ns" {  } { { "db/cntr_p78.tdf" "" { Text "F:/quartus/演示程序/lcd_zifu/db/cntr_p78.tdf" 77 8 0 } }  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.647 ns" { lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] lcd:mylcd|count[3]~439 lcd:mylcd|count[3]~440 lcd:mylcd|count[3]~442 lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.647 ns" { lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] lcd:mylcd|count[3]~439 lcd:mylcd|count[3]~440 lcd:mylcd|count[3]~442 lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } { 0.000ns 2.160ns 0.545ns 1.811ns 0.700ns } { 0.000ns 0.755ns 0.204ns 0.204ns 1.268ns } } } { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } } { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lcd:mylcd\|lcd_data\[0\] reset clk -0.325 ns register " "Info: tsu for register \"lcd:mylcd\|lcd_data\[0\]\" (data pin = \"reset\", clock pin = \"clk\") is -0.325 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.261 ns + Longest pin register " "Info: + Longest pin to register delay is 7.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_38 19 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_38; Fanout = 19; PIN Node = 'reset'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { reset } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.861 ns) + CELL(1.268 ns) 7.261 ns lcd:mylcd\|lcd_data\[0\] 2 REG LC_X16_Y5_N2 1 " "Info: 2: + IC(4.861 ns) + CELL(1.268 ns) = 7.261 ns; Loc. = LC_X16_Y5_N2; Fanout = 1; REG Node = 'lcd:mylcd\|lcd_data\[0\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "6.129 ns" { reset lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns 33.05 % " "Info: Total cell delay = 2.400 ns ( 33.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.861 ns 66.95 % " "Info: Total interconnect delay = 4.861 ns ( 66.95 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.261 ns" { reset lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.261 ns" { reset reset~combout lcd:mylcd|lcd_data[0] } { 0.000ns 0.000ns 4.861ns } { 0.000ns 1.132ns 1.268ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.180 ns + " "Info: + Micro setup delay of destination is 0.180 ns" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.766 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.321 ns) 4.222 ns clockdiv:div\|clockout 2 REG LC_X12_Y3_N9 21 " "Info: 2: + IC(1.738 ns) + CELL(1.321 ns) = 4.222 ns; Loc. = LC_X12_Y3_N9; Fanout = 21; REG Node = 'clockdiv:div\|clockout'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.059 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.607 ns) + CELL(0.937 ns) 7.766 ns lcd:mylcd\|lcd_data\[0\] 3 REG LC_X16_Y5_N2 1 " "Info: 3: + IC(2.607 ns) + CELL(0.937 ns) = 7.766 ns; Loc. = LC_X16_Y5_N2; Fanout = 1; REG Node = 'lcd:mylcd\|lcd_data\[0\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "3.544 ns" { clockdiv:div|clockout lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.421 ns 44.05 % " "Info: Total cell delay = 3.421 ns ( 44.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.345 ns 55.95 % " "Info: Total interconnect delay = 4.345 ns ( 55.95 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lcd_data[0] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.261 ns" { reset lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.261 ns" { reset reset~combout lcd:mylcd|lcd_data[0] } { 0.000ns 0.000ns 4.861ns } { 0.000ns 1.132ns 1.268ns } } } { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "7.766 ns" { clk clockdiv:div|clockout lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/qprogrammer/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lcd_data[0] } { 0.000ns 0.000ns 1.738ns 2.607ns } { 0.000ns 1.163ns 1.321ns 0.937ns } } }  } 0}