lcdcont.fit.qmsg

关于lcd的vhdl程序代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 26 16:49:12 2005 " "Info: Processing started: Wed Oct 26 16:49:12 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off lcdcont -c lcdcont " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off lcdcont -c lcdcont" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "lcdcont EPM1270T144C5ES " "Info: Selected device EPM1270T144C5ES for design \"lcdcont\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Info: Device EPM570T144C5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144C5 " "Info: Device EPM1270T144C5 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 18 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 18" {  } { { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 9 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clockdiv:div\|clockout Global clock " "Info: Automatically promoted some destinations of signal \"clockdiv:div\|clockout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "enable_out " "Info: Destination \"enable_out\" may be non-global or may not use global clock" {  } { { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 14 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clockdiv:div\|clockout " "Info: Destination \"clockdiv:div\|clockout\" may be non-global or may not use global clock" {  } { { "clockdiv.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0}  } { { "clockdiv.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[4\] " "Info: Destination \"lcd:mylcd\|lcd_data\[4\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[3\] " "Info: Destination \"lcd:mylcd\|lcd_data\[3\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[2\] " "Info: Destination \"lcd:mylcd\|lcd_data\[2\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[1\] " "Info: Destination \"lcd:mylcd\|lcd_data\[1\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[0\] " "Info: Destination \"lcd:mylcd\|lcd_data\[0\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[6\] " "Info: Destination \"lcd:mylcd\|lcd_data\[6\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[5\] " "Info: Destination \"lcd:mylcd\|lcd_data\[5\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_select " "Info: Destination \"lcd:mylcd\|lcd_select\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 17 -1 0 } }  } 0}  } { { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 10 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "reset " "Info: Pin \"reset\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 10 -1 0 } } { "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/qprogrammer/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { reset } "NODE_NAME" } "" } } { "F:/quartus/演示程序/lcd_zifu/lcdcont.fld" "" { Floorplan "F:/quartus/演示程序/lcd_zifu/lcdcont.fld" "" "" { reset } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.906 ns register pin " "Info: Estimated most critical path is register to pin delay of 2.906 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:mylcd\|lcd_data\[0\] 1 REG LAB_X16_Y5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y5; Fanout = 1; REG Node = 'lcd:mylcd\|lcd_data\[0\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "" { lcd:mylcd|lcd_data[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.584 ns) + CELL(2.322 ns) 2.906 ns data_out\[0\] 2 PIN PIN_91 0 " "Info: 2: + IC(0.584 ns) + CELL(2.322 ns) = 2.906 ns; Loc. = PIN_91; Fanout = 0; PIN Node = 'data_out\[0\]'" {  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "2.906 ns" { lcd:mylcd|lcd_data[0] data_out[0] } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "F:/quartus/演示程序/lcd_zifu/lcdcont.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 79.90 % " "Info: Total cell delay = 2.322 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.584 ns 20.10 % " "Info: Total interconnect delay = 0.584 ns ( 20.10 % )" {  } {  } 0}  } { { "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "F:/quartus/演示程序/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "F:/quartus/演示程序/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "F:/quartus/演示程序/lcd_zifu/" "" "2.906 ns" { lcd:mylcd|lcd_data[0] data_out[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 26 16:49:16 2005 " "Info: Processing ended: Wed Oct 26 16:49:16 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}