lcdcont.vhd

关于lcd的vhdl程序代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;

entity lcdcont is
	generic ( asciiwidth : positive := 8);
	
	port (	clk 		: in std_logic;         -- 2.5 kHz
		    reset 		: in std_logic;  
		    data_out 	: out std_logic_vector(asciiwidth-1 downto 0); -- lcd data   
	        rw_out,cont 		: out std_logic;      	-- lcd read(1)/write(0) line
		    select_out 	: out std_logic;  		-- lcd select (0=data, 1=instruction)
		    enable_out 	: out std_logic  		-- lcd enable line - must be pulsed!
		);
end lcdcont;

architecture structural of lcdcont is

component lcd
	port 
	(	clk        : in std_logic;
		reset      : in std_logic;
		data_valid : in std_logic;    -- causes lcd to start new write cycle when high
		lcd_data   : out std_logic_vector(asciiwidth-1 downto 0);
		lcd_select : out std_logic;
		lcd_rw     : out std_logic;
		lcd_enable : out std_logic;
		done       : out std_logic
	);  	-- set low during write cycle, high if ready for new data
		
end component;


component clockdiv
	port(
    	clockin : in std_logic;
    	clockout : out std_logic );
end component;



signal valid_int, enable_int, reset_int, done_int, rw_int : std_logic;
signal small_clk : std_logic;

begin

enable_out <= enable_int;
display : process(small_clk)
	begin
	if reset = '0' then
		valid_int <= '1';
	elsif rising_edge(small_clk) then
		if done_int = '1' then
			valid_int <= '1';	
		else
			valid_int <= '0';
		end if;
	end if;
end process;

cont<='0';

mylcd : lcd port map(
	clk => small_clk,
	reset => reset,
	data_valid => valid_int,
	lcd_data => data_out,
	lcd_select => select_out,
	lcd_rw => rw_out,
	lcd_enable => enable_int,
	done => done_int);


div : clockdiv port map(
	clockin => clk,
	clockout => small_clk);

end structural;