lcdcont.tan.rpt

关于lcd的vhdl程序代码

; Worst-case th                ; N/A   ; None          ; 1.176 ns                         ; reset                                                               ; lcd:mylcd|lcd_data[1]                                               ;            ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 121.79 MHz ( period = 8.211 ns ) ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[3] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                     ;                                                                     ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM1270T144C5ES    ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                ; To                                                                  ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 121.79 MHz ( period = 8.211 ns )                    ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[0] ; clk        ; clk      ; None                        ; None                      ; 7.647 ns                ;
; N/A                                     ; 121.79 MHz ( period = 8.211 ns )                    ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] ; clk        ; clk      ; None                        ; None                      ; 7.647 ns                ;
; N/A                                     ; 121.79 MHz ( period = 8.211 ns )                    ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[1] ; clk        ; clk      ; None                        ; None                      ; 7.647 ns                ;
; N/A                                     ; 121.79 MHz ( period = 8.211 ns )                    ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[2] ; lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated|safe_q[3] ; clk        ; clk      ; None                        ; None                      ; 7.647 ns                ;
; N/A                                     ; 124.16 MHz ( period = 8.054 ns )                    ; clockdiv:div|\count:counter[8]                                      ; clockdiv:div|clockout                                               ; clk        ; clk      ; None                        ; None                      ; 7.490 ns                ;