📄 lcdcont.fit.rpt
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+---------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; C4s ; 23 / 2,870 ( < 1 % ) ;
; Direct links ; 27 / 3,938 ( < 1 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
; LAB clocks ; 10 / 72 ( 13 % ) ;
; LUT chains ; 4 / 1,143 ( < 1 % ) ;
; Local interconnects ; 72 / 3,938 ( 1 % ) ;
; R4s ; 31 / 2,832 ( 1 % ) ;
+----------------------------+----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 6.50) ; Number of LABs (Total = 10) ;
+--------------------------------------------+------------------------------+
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 4 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.60) ; Number of LABs (Total = 10) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 3 ;
; 1 Clock ; 10 ;
; 1 Clock enable ; 3 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.10) ; Number of LABs (Total = 10) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 2 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 3 ;
; 11 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.30) ; Number of LABs (Total = 10) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 2 ;
; 6 ; 3 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 7.90) ; Number of LABs (Total = 10) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 1 ;
; 12 ; 1 ;
; 13 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Wed Oct 26 16:49:12 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off lcdcont -c lcdcont
Info: Selected device EPM1270T144C5ES for design "lcdcont"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM1270T144C5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "clockdiv:div|clockout" to use Global clock
Info: Destination "enable_out" may be non-global or may not use global clock
Info: Destination "clockdiv:div|clockout" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "reset" to use Global clock
Info: Destination "lcd:mylcd|lcd_data[4]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[3]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[2]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[1]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[0]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[6]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[5]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_select" may be non-global or may not use global clock
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 2.906 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y5; Fanout = 1; REG Node = 'lcd:mylcd|lcd_data[0]'
Info: 2: + IC(0.584 ns) + CELL(2.322 ns) = 2.906 ns; Loc. = PIN_91; Fanout = 0; PIN Node = 'data_out[0]'
Info: Total cell delay = 2.322 ns ( 79.90 % )
Info: Total interconnect delay = 0.584 ns ( 20.10 % )
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Oct 26 16:49:16 2005
Info: Elapsed time: 00:00:05
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