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📄 lcdcont.map.rpt

📁 关于lcd的vhdl程序代码
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+---------------+-------------+------------+------------+---------------+-------------+---------------+---------------+--------------+
; Name          ; state.write ; state.idle ; state.home ; state.setmode ; state.clear ; state.dispoff ; state.setfunc ; state.warmup ;
+---------------+-------------+------------+------------+---------------+-------------+---------------+---------------+--------------+
; state.warmup  ; 0           ; 0          ; 0          ; 0             ; 0           ; 0             ; 0             ; 0            ;
; state.setfunc ; 0           ; 0          ; 0          ; 0             ; 0           ; 0             ; 1             ; 1            ;
; state.dispoff ; 0           ; 0          ; 0          ; 0             ; 0           ; 1             ; 0             ; 1            ;
; state.clear   ; 0           ; 0          ; 0          ; 0             ; 1           ; 0             ; 0             ; 1            ;
; state.setmode ; 0           ; 0          ; 0          ; 1             ; 0           ; 0             ; 0             ; 1            ;
; state.home    ; 0           ; 0          ; 1          ; 0             ; 0           ; 0             ; 0             ; 1            ;
; state.idle    ; 0           ; 1          ; 0          ; 0             ; 0           ; 0             ; 0             ; 1            ;
; state.write   ; 1           ; 0          ; 0          ; 0             ; 0           ; 0             ; 0             ; 1            ;
+---------------+-------------+------------+------------+---------------+-------------+---------------+---------------+--------------+


+-----------+
; Hierarchy ;
+-----------+
lcdcont
 |-- clockdiv:div
 |-- lcd:mylcd
      |-- lpm_counter:count_rtl_0
           |-- cntr_p78:auto_generated


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                             ;
+------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------+
; Compilation Hierarchy Node         ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                ;
+------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------+
; |lcdcont                           ; 71 (0)      ; 35           ; 0          ; 14   ; 0            ; 36 (0)       ; 11 (0)            ; 24 (0)           ; 19 (0)          ; |lcdcont                                                           ;
;    |clockdiv:div|                  ; 36 (36)     ; 16           ; 0          ; 0    ; 0            ; 20 (20)      ; 9 (9)             ; 7 (7)            ; 15 (15)         ; |lcdcont|clockdiv:div                                              ;
;    |lcd:mylcd|                     ; 35 (31)     ; 19           ; 0          ; 0    ; 0            ; 16 (16)      ; 2 (2)             ; 17 (13)          ; 4 (0)           ; |lcdcont|lcd:mylcd                                                 ;
;       |lpm_counter:count_rtl_0|    ; 4 (0)       ; 4            ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |lcdcont|lcd:mylcd|lpm_counter:count_rtl_0                         ;
;          |cntr_p78:auto_generated| ; 4 (4)       ; 4            ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |lcdcont|lcd:mylcd|lpm_counter:count_rtl_0|cntr_p78:auto_generated ;
+------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/quartus/演示程序/lcd_zifu/lcdcont.map.eqn.


+------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                   ;
+----------------------------------+-----------------+-------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                                        ;
+----------------------------------+-----------------+-------------------------------------------------------------------------------------+
; clockdiv.vhd                     ; yes             ; F:/quartus/演示程序/lcd_zifu/clockdiv.vhd                                           ;
; lcd.vhd                          ; yes             ; F:/quartus/演示程序/lcd_zifu/lcd.vhd                                                ;
; lcdcont.vhd                      ; yes             ; F:/quartus/演示程序/lcd_zifu/lcdcont.vhd                                            ;
; lpm_counter.tdf                  ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc                    ; yes             ; d:/program files/altera/qprogrammer/libraries/megafunctions/aglobal42.inc           ;
; db/cntr_p78.tdf                  ; yes             ; F:/quartus/演示程序/lcd_zifu/db/cntr_p78.tdf                                        ;
+----------------------------------+-----------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary               ;
+-----------------------------------+-----------------------+
; Resource                          ; Usage                 ;
+-----------------------------------+-----------------------+
; Logic cells                       ; 71                    ;
; Total combinational functions     ; 60                    ;
; Total 4-input functions           ; 18                    ;
; Total 3-input functions           ; 12                    ;
; Total 2-input functions           ; 9                     ;
; Total 1-input functions           ; 19                    ;
; Total 0-input functions           ; 2                     ;
; Combinational cells for routing   ; 0                     ;
; Total registers                   ; 35                    ;
; Total logic cells in carry chains ; 19                    ;
; I/O pins                          ; 14                    ;
; Maximum fan-out node              ; clockdiv:div|clockout ;
; Maximum fan-out                   ; 21                    ;
; Total fan-out                     ; 247                   ;
; Average fan-out                   ; 2.91                  ;
+-----------------------------------+-----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Oct 26 16:49:06 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off lcdcont -c lcdcont
Info: Found 2 design units, including 1 entities, in source file clockdiv.vhd
    Info: Found design unit 1: clockdiv-behavioural
    Info: Found entity 1: clockdiv
Info: Found 2 design units, including 1 entities, in source file lcd.vhd
    Info: Found design unit 1: lcd-behavioural
    Info: Found entity 1: lcd
Info: Found 2 design units, including 1 entities, in source file lcdcont.vhd
    Info: Found design unit 1: lcdcont-structural
    Info: Found entity 1: lcdcont
Warning: VHDL Process Statement warning at lcdcont.vhd(51): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at lcd.vhd(168): OTHERS choice is never selected
Warning: Reduced register "lcd:mylcd|lcd_rw" with stuck data_in port to stuck value GND
Info: Power-up level of register "lcd:mylcd|write_mode" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "lcd:mylcd|write_mode" with stuck data_in port to stuck value VCC
Warning: Reduced register "lcd:mylcd|lcd_data[7]" with stuck data_in port to stuck value GND
Info: State machine "|lcdcont|lcd:mylcd|state" contains 8 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|lcdcont|lcd:mylcd|state"
Info: Encoding result for state machine "|lcdcont|lcd:mylcd|state"
    Info: Completed encoding using 8 state bits
        Info: Encoded state bit "lcd:mylcd|state.write"
        Info: Encoded state bit "lcd:mylcd|state.idle"
        Info: Encoded state bit "lcd:mylcd|state.home"
        Info: Encoded state bit "lcd:mylcd|state.setmode"
        Info: Encoded state bit "lcd:mylcd|state.clear"
        Info: Encoded state bit "lcd:mylcd|state.dispoff"
        Info: Encoded state bit "lcd:mylcd|state.setfunc"
        Info: Encoded state bit "lcd:mylcd|state.warmup"
    Info: State "|lcdcont|lcd:mylcd|state.warmup" uses code string "00000000"
    Info: State "|lcdcont|lcd:mylcd|state.setfunc" uses code string "00000011"
    Info: State "|lcdcont|lcd:mylcd|state.dispoff" uses code string "00000101"
    Info: State "|lcdcont|lcd:mylcd|state.clear" uses code string "00001001"
    Info: State "|lcdcont|lcd:mylcd|state.setmode" uses code string "00010001"
    Info: State "|lcdcont|lcd:mylcd|state.home" uses code string "00100001"
    Info: State "|lcdcont|lcd:mylcd|state.idle" uses code string "01000001"
    Info: State "|lcdcont|lcd:mylcd|state.write" uses code string "10000001"
Warning: Reduced register "lcd:mylcd|state.idle" with stuck data_in port to stuck value GND
Warning: No clock transition on "lcd:mylcd|last_data_valid" register
Warning: Reduced register "lcd:mylcd|last_data_valid" with stuck clock port to stuck value GND
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "lcd:mylcd|count[0]~37"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/qprogrammer/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_p78.tdf
    Info: Found entity 1: cntr_p78
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "data_out[7]" stuck at GND
    Warning: Pin "rw_out" stuck at GND
    Warning: Pin "cont" stuck at GND
Info: Implemented 85 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 12 output pins
    Info: Implemented 71 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Processing ended: Wed Oct 26 16:49:10 2005
    Info: Elapsed time: 00:00:05


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