fifo_example2.v

用Verilog语言写的FPGA FIFO

//1．1．1顶层模块fifo源代码：fifo.v
module fifo (rdata, full, empty, wdata,winc, wclk, rinc, rclk, rst_n);
  parameter DSIZE = 8;
  parameter ASIZE = 4;
  output [DSIZE-1:0] rdata;
  output full;
  output empty;
  input [DSIZE-1:0] wdata;
  input winc, wclk;
  input rinc, rclk, rst_n;
  wire [ASIZE-1:0] wptr, rptr;
//实例化各子模块，调用各子模块
  comp #(ASIZE) comp(.empty(empty),.full(full),.rptr(rptr),.wptr(wptr),
                     .rstate(rstate),.wstate(wstate), .rst_n(rst_n));
  
  brptr #(ASIZE) brptr(.rptr(rptr),.rstate(rstate),.rclk(rclk),
                       .empty(empty),.rst_n(rst_n),.rinc(rinc));
  
  bwptr #(ASIZE) bwptr (.wptr(wptr),.wstate(wstate),.wclk(wclk),
                        .full(full),.rst_n(rst_n),.winc(winc));
  
  fifomem #(DSIZE, ASIZE) fifomem (.rdata(rdata), .wdata(wdata),.waddr(wptr), 
                                   .raddr(rptr), .wclken(winc), .wclk(wclk));
endmodule

//1．1．2双口RAM存储器模块fifomem源代码：fifomem.v
module fifomem (rdata, wdata, waddr, raddr, wclken, wclk);
  parameter DATASIZE = 8; // Memory data word width
  parameter ADDRSIZE = 4; // Number of memory address bits
  parameter DEPTH = 1<<ADDRSIZE; // DEPTH = 2**ADDRSIZE
  output [DATASIZE-1:0] rdata;
  input [DATASIZE-1:0] wdata;
  input [ADDRSIZE-1:0] waddr, raddr;
  input wclken, wclk;

  `ifdef VENDORRAM
// instantiation of a vendor's dual-port RAM
      VENDOR_RAM MEM (.dout(rdata), .din(wdata),
                    .waddr(waddr), .raddr(raddr),
                    .wclken(wclken), .clk(wclk));
  `else
  reg [DATASIZE-1:0] MEM [0:DEPTH-1];
  assign rdata = MEM[raddr];

  always @(posedge wclk)
      if (wclken)
         MEM[waddr] <= wdata;
 `endif
endmodule

//1．1．3写地址和写状态位产生模块bwptr源代码：bwptr.v
module bwptr (wptr,wstate,wclk,full,rst_n,winc);
  parameter size=4;
  output [size-1:0] wptr; 
  output wstate;
  input wclk,rst_n,full,winc;
  reg [size-1:0] wgray;
  reg [size:0] wbin5;
  wire [size:0] wbnext5;
  wire [size-1:0] wgnext,wbnext;
  wire [size-1:0] wptr;
  reg wstate;
  
  always @ (posedge wclk or negedge rst_n)
      begin
          if(!rst_n)  
              begin 
                  wbin5<=0;
                  wgray<=0;
                  wgray[size-1:0] <=0;
                  wstate <=0;         
              end
          else 
              begin 
                  wbin5<=wbnext5;
                  wgray<=wgnext;
                  wstate <= wbnext5[size];   //use the msb of bin as wstate
              end
      end 
//---------------------------------------------------------------
// increment the binary count if not full
//---------------------------------------------------------------
  assign wbnext5 = !full ? wbin5 + winc : wbin5;
  assign wbnext = wbnext5[size-1:0];
  assign wgnext = (wbnext>>1) ^ wbnext; // binary-to-gray conversion
  assign wptr[size-1:0] = wgray[size-1:0];//use gray as the address of write data
endmodule

//1．1．4读地址和读状态位产生模块brptr源代码：brptr.v
module brptr (rptr,rstate,rclk,empty,rst_n,rinc);
  parameter size=4;
  output [size-1:0] rptr; 
  output rstate;
  input rclk,rst_n,empty,rinc;
  reg [size-1:0] rgray;
  reg [size:0] rbin5;
  wire [size:0] rbnext5;
  wire [size-1:0] rgnext,rbnext;
  wire [size-1:0] rptr;
  reg rstate;
  
  always @ (posedge rclk or negedge rst_n)
      begin
          if(!rst_n)  
              begin 
                  rbin5<=0;
                  rgray<=0;
                  rgray[size-1:0] <=0;
                  rstate <=0;          
              end
          else 
              begin 
                  rbin5<=rbnext5;
                  rgray<=rgnext;
                  rstate <= rbnext5[size];   //use the msb of bin as rstate
              end
      end 
//---------------------------------------------------------------
// increment the binary count if not empty
//---------------------------------------------------------------
  assign rbnext5 = !empty ? rbin5 + rinc : rbin5;
  assign rbnext = rbnext5[size-1:0];
  assign rgnext = (rbnext>>1) ^ rbnext; // binary-to-gray conversion
  assign rptr[size-1:0] = rgray[size-1:0];//use gray as the address of read data
endmodule
    
//1．1．4读写地址比较模块comp源代码：comp.v
module comp (empty,full,rptr,wptr,rstate,wstate,rst_n);
  parameter size=4 ;
  input [size-1:0] rptr,wptr;	
  input rstate,wstate,rst_n;
  output empty,full;
  reg empty,full;
  
  always @ ( wptr or rptr)
    if (!rst_n) 
        begin 
            empty<=1;
            full<=0;
        end      
    else if((rptr==wptr)&&(rstate!=wstate)) //if address are the same but state are not the same.full is true
         full<=1;
      
    else if ((rptr==wptr)&&(rstate==wstate)) //if state and address both are the same ,empty is true  
         empty<=1;
    else 
    	begin
         	  empty <=0;
            full <=0;
        end
endmodule