stbc.txt

stbc空时编码源码

module stbc(datain_i,datain_q,dataout_i1,dataout_q1,dataout_i2,dataout_q2,clk,rst,enable);
output [2:0] dataout_i1,dataout_i2,dataout_q1,dataout_q2;
input [2:0] datain_i,datain_q;
input clk,rst,enable;
reg [2:0] dataout_i1,dataout_i2,dataout_q1,dataout_q2;
reg [2:0] reg_i1,reg_q1,reg_i2,reg_q2;
reg [2:0] reg_i3,reg_q3,reg_i4,reg_q4;
reg clk_i;
integer count;
initial
begin
dataout_i1<=0;
dataout_i2<=0; 
dataout_q1<=0;
dataout_q2<=0;
reg_i1<=0;
reg_i2<=0;
reg_i3<=0;
reg_i4<=0;
reg_q1<=0;
reg_q2<=0;
reg_q3<=0;
reg_q4<=0;
clk_i<=1;
count<=0;
end

//if(enable)begin
always @ (posedge clk)begin
//if(rst)begin
//dataout_i1<=0;
//dataout_i2<=0;
//dataout_q1<=0;
//dataout_q2<=0;
//reg_i1<=0;
//reg_i2<=0;
//reg_q1<=0;
//reg_q2<=0;
//clk_i<=1;
//count<=0;
//end
if(enable)begin
//if(count==100)begin
reg_i2<=reg_i1;
reg_q2<=reg_q1;
reg_i1<=datain_i;
reg_q1<=datain_q;
clk_i<=~clk_i;
//count<=0;
//enable<=0;
if(clk_i==0)begin
dataout_i1<=reg_i1;
dataout_q1<=reg_q1;
dataout_i2<=reg_i2;
dataout_q2<=reg_q2;
reg_i3<=reg_i1;
reg_q3<=reg_q1;
reg_i4<=reg_i2;
reg_q4<=reg_q2;
end
else
begin
dataout_i1<={~reg_i4[2],reg_i4[1:0]};
dataout_q1<=reg_q4;
dataout_i2<=reg_i3;
dataout_q2<={~reg_q3[2],reg_q3[1:0]};
end
//end
//else 
//count<=count+1;
end
end
endmodule