encode.map.summary

这是一个verilog源码的优先编码器

Flow Status : Successful - Sat Feb 11 16:28:07 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : encode
Top-level Entity Name : encode
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 14
Total pins : 24
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0