encode.fit.qmsg

这是一个verilog源码的优先编码器

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "9 " "Warning: The following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "c\[0\] VCC " "Info: Pin c\[0\] has VCC driving its datain port" {  } { { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "c\[0\]" } } } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { c[0] } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" "" { c[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[0\] GND " "Info: Pin en\[0\] has GND driving its datain port" {  } { { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[0\]" } } } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { en[0] } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" "" { en[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[1\] VCC " "Info: Pin en\[1\] has VCC driving its datain port" {  } { { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[1\]" } } } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { en[1] } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" "" { en[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[2\] VCC " "Info: Pin en\[2\] has VCC driving its datain port" {  } { { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[2\]" } } } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { en[2] } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" "" { en[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[3\] VCC " "Info: Pin en\[3\] has VCC driving its datain port" {  } { { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[3\]" } } } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { en[3] } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" "" { en[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[4\] VCC " "Info: Pin en\[4\] has VCC driving its datain port" {  } { { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[4\]" } } } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { en[4] } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" "" { en[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[5\] VCC " "Info: Pin en\[5\] has VCC driving its datain port" {  } { { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[5\]" } } } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { en[5] } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" "" { en[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[6\] VCC " "Info: Pin en\[6\] has VCC driving its datain port" {  } { { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[6\]" } } } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { en[6] } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" "" { en[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[7\] VCC " "Info: Pin en\[7\] has VCC driving its datain port" {  } { { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[7\]" } } } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { en[7] } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.fld" "" "" { en[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 11 16:28:11 2006 " "Info: Processing ended: Sat Feb 11 16:28:11 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}