encode.tan.qmsg

这是一个verilog源码的优先编码器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 11 16:28:15 2006 " "Info: Processing started: Sat Feb 11 16:28:15 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[4\] c\[3\] 15.811 ns Longest " "Info: Longest tpd from source pin \"a\[4\]\" to destination pin \"c\[3\]\" is 15.811 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns a\[4\] 1 PIN PIN_99 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_99; Fanout = 5; PIN Node = 'a\[4\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { a[4] } "NODE_NAME" } "" } } { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.166 ns) + CELL(0.590 ns) 7.225 ns c_tmp~366 2 COMB LC_X26_Y11_N4 1 " "Info: 2: + IC(5.166 ns) + CELL(0.590 ns) = 7.225 ns; Loc. = LC_X26_Y11_N4; Fanout = 1; COMB Node = 'c_tmp~366'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "5.756 ns" { a[4] c_tmp~366 } "NODE_NAME" } "" } } { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.163 ns) + CELL(0.442 ns) 8.830 ns c_tmp~367 3 COMB LC_X26_Y12_N9 4 " "Info: 3: + IC(1.163 ns) + CELL(0.442 ns) = 8.830 ns; Loc. = LC_X26_Y12_N9; Fanout = 4; COMB Node = 'c_tmp~367'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "1.605 ns" { c_tmp~366 c_tmp~367 } "NODE_NAME" } "" } } { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(0.590 ns) 9.880 ns reduce_or~513 4 COMB LC_X26_Y12_N4 1 " "Info: 4: + IC(0.460 ns) + CELL(0.590 ns) = 9.880 ns; Loc. = LC_X26_Y12_N4; Fanout = 1; COMB Node = 'reduce_or~513'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "1.050 ns" { c_tmp~367 reduce_or~513 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.807 ns) + CELL(2.124 ns) 15.811 ns c\[3\] 5 PIN PIN_2 0 " "Info: 5: + IC(3.807 ns) + CELL(2.124 ns) = 15.811 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'c\[3\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "5.931 ns" { reduce_or~513 c[3] } "NODE_NAME" } "" } } { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.215 ns 32.98 % " "Info: Total cell delay = 5.215 ns ( 32.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.596 ns 67.02 % " "Info: Total interconnect delay = 10.596 ns ( 67.02 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/EP1C3/示例程序/veriloge/基础实验/8位优先编码器/" "" "15.811 ns" { a[4] c_tmp~366 c_tmp~367 reduce_or~513 c[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "15.811 ns" { a[4] a[4]~out0 c_tmp~366 c_tmp~367 reduce_or~513 c[3] } { 0.000ns 0.000ns 5.166ns 1.163ns 0.460ns 3.807ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 11 16:28:15 2006 " "Info: Processing ended: Sat Feb 11 16:28:15 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}