📄 alarm.rpt
字号:
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 21 AND2 s 4 0 0 1 ~416~1
- 3 - C 21 AND2 s 3 1 0 1 ~416~2
- 4 - C 21 OR2 s 4 0 0 1 ~416~3
- 2 - C 23 AND2 s 4 0 0 1 ~416~4
- 1 - C 23 AND2 s 3 1 0 1 ~416~5
- 5 - C 21 AND2 s 4 0 0 1 ~416~6
- 6 - C 21 AND2 s 3 0 0 1 ~416~7
- 7 - C 21 AND2 s 2 2 0 1 ~416~8
- 1 - C 21 OR2 0 4 1 0 :416
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\11111111111111\max+plus\clock\alarm.rpt
alarm
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 8/ 96( 8%) 0/ 48( 0%) 6/ 48( 12%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\11111111111111\max+plus\clock\alarm.rpt
alarm
** EQUATIONS **
clk1 : INPUT;
clk2 : INPUT;
min0 : INPUT;
min1 : INPUT;
min2 : INPUT;
min3 : INPUT;
min4 : INPUT;
min5 : INPUT;
min6 : INPUT;
min7 : INPUT;
sec0 : INPUT;
sec1 : INPUT;
sec2 : INPUT;
sec3 : INPUT;
sec4 : INPUT;
sec5 : INPUT;
sec6 : INPUT;
sec7 : INPUT;
-- Node name is 'qout'
-- Equation name is 'qout', type is output
qout = _LC1_C21;
-- Node name is '~416~1'
-- Equation name is '~416~1', location is LC2_C21, type is buried.
-- synthesized logic cell
_LC2_C21 = LCELL( _EQ001);
_EQ001 = clk1 & min4 & min6 & sec4;
-- Node name is '~416~2'
-- Equation name is '~416~2', location is LC3_C21, type is buried.
-- synthesized logic cell
_LC3_C21 = LCELL( _EQ002);
_EQ002 = _LC2_C21 & min0 & min3 & sec6;
-- Node name is '~416~3'
-- Equation name is '~416~3', location is LC4_C21, type is buried.
-- synthesized logic cell
_LC4_C21 = LCELL( _EQ003);
_EQ003 = !sec3
# !sec1 & !sec2 & sec6;
-- Node name is '~416~4'
-- Equation name is '~416~4', location is LC2_C23, type is buried.
-- synthesized logic cell
_LC2_C23 = LCELL( _EQ004);
_EQ004 = !min1 & !min2 & !min5 & !min7;
-- Node name is '~416~5'
-- Equation name is '~416~5', location is LC1_C23, type is buried.
-- synthesized logic cell
_LC1_C23 = LCELL( _EQ005);
_EQ005 = _LC2_C23 & !sec0 & !sec5 & !sec7;
-- Node name is '~416~6'
-- Equation name is '~416~6', location is LC5_C21, type is buried.
-- synthesized logic cell
_LC5_C21 = LCELL( _EQ006);
_EQ006 = !min0 & !min3 & !min4 & !min6;
-- Node name is '~416~7'
-- Equation name is '~416~7', location is LC6_C21, type is buried.
-- synthesized logic cell
_LC6_C21 = LCELL( _EQ007);
_EQ007 = clk2 & !sec1 & !sec2;
-- Node name is '~416~8'
-- Equation name is '~416~8', location is LC7_C21, type is buried.
-- synthesized logic cell
_LC7_C21 = LCELL( _EQ008);
_EQ008 = _LC5_C21 & _LC6_C21 & !sec4 & !sec6;
-- Node name is ':416'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ009);
_EQ009 = _LC1_C23 & _LC3_C21 & _LC4_C21
# _LC1_C23 & _LC4_C21 & _LC7_C21;
Project Information d:\11111111111111\max+plus\clock\alarm.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,190K
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