clock60.rpt

以前学习VHDL语言时做的一个电子闹钟程序

_LC2_C18 = DFFE( _EQ015,  _LC3_C18, GLOBAL( rst2),  VCC,  VCC);
  _EQ015 = !_LC1_C18 &  _LC2_C18 & !_LC7_C18
         #  _LC1_C18 & !_LC2_C18 & !_LC7_C18;

-- Node name is '|CNT24:36|:14' = '|CNT24:36|ql2' 
-- Equation name is '_LC6_C18', type is buried 
_LC6_C18 = DFFE( _EQ016,  _LC3_C18, GLOBAL( rst2),  VCC,  VCC);
  _EQ016 =  _LC6_C18 & !_LC7_C18 & !_LC8_C18
         # !_LC6_C18 & !_LC7_C18 &  _LC8_C18;

-- Node name is '|CNT24:36|:13' = '|CNT24:36|ql3' 
-- Equation name is '_LC5_C18', type is buried 
_LC5_C18 = DFFE( _EQ017,  _LC3_C18, GLOBAL( rst2),  VCC,  VCC);
  _EQ017 =  _LC5_C18 & !_LC6_C18 & !_LC7_C18
         #  _LC5_C18 & !_LC7_C18 & !_LC8_C18
         # !_LC5_C18 &  _LC6_C18 & !_LC7_C18 &  _LC8_C18;

-- Node name is '|CNT24:36|:3' 
-- Equation name is '_LC1_C23', type is buried 
_LC1_C23 = DFFE( _EQ018,  _LC3_C18, GLOBAL( rst2),  VCC,  VCC);
  _EQ018 =  _LC2_C23 &  _LC7_C18
         #  _LC1_C23 & !_LC7_C18;

-- Node name is '|CNT24:36|:95' 
-- Equation name is '_LC7_C18', type is buried 
!_LC7_C18 = _LC7_C18~NOT;
_LC7_C18~NOT = LCELL( _EQ019);
  _EQ019 = !_LC8_C18
         #  _LC5_C18
         #  _LC6_C18;

-- Node name is '|CNT24:36|:113' 
-- Equation name is '_LC2_C23', type is buried 
!_LC2_C23 = _LC2_C23~NOT;
_LC2_C23~NOT = LCELL( _EQ020);
  _EQ020 =  _LC7_C23
         #  _LC4_C23
         #  _LC3_C23
         # !_LC5_C23;

-- Node name is '|CNT60:2|LPM_ADD_SUB:140|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A17', type is buried 
_LC6_A17 = LCELL( _EQ021);
  _EQ021 =  _LC1_A17 &  _LC8_A17;

-- Node name is '|CNT60:2|LPM_ADD_SUB:140|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A17', type is buried 
_LC7_A17 = LCELL( _EQ022);
  _EQ022 =  _LC1_A17 &  _LC5_A17 &  _LC8_A17;

-- Node name is '|CNT60:2|:20' = '|CNT60:2|qh0' 
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = DFFE( _EQ023, GLOBAL( cp), GLOBAL( rst),  VCC,  VCC);
  _EQ023 =  _LC1_A17 & !_LC8_A24
         # !_LC1_A17 &  _LC8_A24;

-- Node name is '|CNT60:2|:19' = '|CNT60:2|qh1' 
-- Equation name is '_LC8_A17', type is buried 
_LC8_A17 = DFFE( _EQ024, GLOBAL( cp), GLOBAL( rst),  VCC,  VCC);
  _EQ024 = !_LC1_A17 & !_LC2_A17 &  _LC8_A17
         #  _LC1_A17 & !_LC2_A17 & !_LC8_A17 &  _LC8_A24
         #  _LC8_A17 & !_LC8_A24;

-- Node name is '|CNT60:2|:18' = '|CNT60:2|qh2' 
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = DFFE( _EQ025, GLOBAL( cp), GLOBAL( rst),  VCC,  VCC);
  _EQ025 = !_LC2_A17 &  _LC5_A17 & !_LC6_A17
         # !_LC2_A17 & !_LC5_A17 &  _LC6_A17 &  _LC8_A24
         #  _LC5_A17 & !_LC8_A24;

-- Node name is '|CNT60:2|:17' = '|CNT60:2|qh3' 
-- Equation name is '_LC3_A17', type is buried 
_LC3_A17 = DFFE( _EQ026, GLOBAL( cp), GLOBAL( rst),  VCC,  VCC);
  _EQ026 = !_LC2_A17 &  _LC3_A17 & !_LC7_A17
         # !_LC2_A17 & !_LC3_A17 &  _LC7_A17 &  _LC8_A24
         #  _LC3_A17 & !_LC8_A24;

-- Node name is '|CNT60:2|:16' = '|CNT60:2|ql0' 
-- Equation name is '_LC1_B12', type is buried 
_LC1_B12 = DFFE(!_LC1_B12, GLOBAL( cp), GLOBAL( rst),  VCC,  VCC);

-- Node name is '|CNT60:2|:15' = '|CNT60:2|ql1' 
-- Equation name is '_LC4_A24', type is buried 
_LC4_A24 = DFFE( _EQ027, GLOBAL( cp), GLOBAL( rst),  VCC,  VCC);
  _EQ027 = !_LC1_B12 &  _LC4_A24 & !_LC8_A24
         #  _LC1_B12 & !_LC4_A24 & !_LC8_A24;

-- Node name is '|CNT60:2|:14' = '|CNT60:2|ql2' 
-- Equation name is '_LC3_A24', type is buried 
_LC3_A24 = DFFE( _EQ028, GLOBAL( cp), GLOBAL( rst),  VCC,  VCC);
  _EQ028 =  _LC3_A24 & !_LC4_A24 & !_LC8_A24
         # !_LC1_B12 &  _LC3_A24 & !_LC8_A24
         #  _LC1_B12 & !_LC3_A24 &  _LC4_A24 & !_LC8_A24;

-- Node name is '|CNT60:2|:13' = '|CNT60:2|ql3' 
-- Equation name is '_LC7_A24', type is buried 
_LC7_A24 = DFFE( _EQ029, GLOBAL( cp), GLOBAL( rst),  VCC,  VCC);
  _EQ029 = !_LC1_B12 &  _LC7_A24
         #  _LC1_B12 &  _LC3_A24 &  _LC4_A24 & !_LC7_A24
         #  _LC3_A24 & !_LC4_A24 &  _LC7_A24
         # !_LC3_A24 &  _LC4_A24 &  _LC7_A24;

-- Node name is '|CNT60:2|:3' 
-- Equation name is '_LC2_A15', type is buried 
_LC2_A15 = DFFE( _EQ030, GLOBAL( cp), GLOBAL( rst),  VCC,  VCC);
  _EQ030 =  _LC2_A17 &  _LC8_A24
         #  _LC2_A15 & !_LC8_A24;

-- Node name is '|CNT60:2|:95' 
-- Equation name is '_LC8_A24', type is buried 
!_LC8_A24 = _LC8_A24~NOT;
_LC8_A24~NOT = LCELL( _EQ031);
  _EQ031 = !_LC1_B12
         # !_LC7_A24
         #  _LC3_A24
         #  _LC4_A24;

-- Node name is '|CNT60:2|:113' 
-- Equation name is '_LC2_A17', type is buried 
_LC2_A17 = LCELL( _EQ032);
  _EQ032 =  _LC1_A17 & !_LC3_A17 &  _LC5_A17 & !_LC8_A17;

-- Node name is '|CNT60:5|LPM_ADD_SUB:140|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ033);
  _EQ033 =  _LC1_A20 &  _LC4_A13;

-- Node name is '|CNT60:5|LPM_ADD_SUB:140|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A15', type is buried 
_LC3_A15 = LCELL( _EQ034);
  _EQ034 =  _LC1_A20 &  _LC2_A20 &  _LC4_A13;

-- Node name is '|CNT60:5|:20' = '|CNT60:5|qh0' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = DFFE( _EQ035,  _LC4_A15, GLOBAL( rst1),  VCC,  VCC);
  _EQ035 =  _LC4_A13 & !_LC6_A13
         # !_LC4_A13 &  _LC6_A13;

-- Node name is '|CNT60:5|:19' = '|CNT60:5|qh1' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = DFFE( _EQ036,  _LC4_A15, GLOBAL( rst1),  VCC,  VCC);
  _EQ036 =  _LC1_A20 & !_LC3_A20 & !_LC4_A13
         # !_LC1_A20 & !_LC3_A20 &  _LC4_A13 &  _LC6_A13
         #  _LC1_A20 & !_LC6_A13;

-- Node name is '|CNT60:5|:18' = '|CNT60:5|qh2' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = DFFE( _EQ037,  _LC4_A15, GLOBAL( rst1),  VCC,  VCC);
  _EQ037 =  _LC2_A20 & !_LC3_A20 & !_LC4_A20
         # !_LC2_A20 & !_LC3_A20 &  _LC4_A20 &  _LC6_A13
         #  _LC2_A20 & !_LC6_A13;

-- Node name is '|CNT60:5|:17' = '|CNT60:5|qh3' 
-- Equation name is '_LC1_A15', type is buried 
_LC1_A15 = DFFE( _EQ038,  _LC4_A15, GLOBAL( rst1),  VCC,  VCC);
  _EQ038 =  _LC1_A15 & !_LC3_A15 & !_LC3_A20
         # !_LC1_A15 &  _LC3_A15 & !_LC3_A20 &  _LC6_A13
         #  _LC1_A15 & !_LC6_A13;

-- Node name is '|CNT60:5|:16' = '|CNT60:5|ql0' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = DFFE(!_LC8_A13,  _LC4_A15, GLOBAL( rst1),  VCC,  VCC);

-- Node name is '|CNT60:5|:15' = '|CNT60:5|ql1' 
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = DFFE( _EQ039,  _LC4_A15, GLOBAL( rst1),  VCC,  VCC);
  _EQ039 = !_LC6_A13 &  _LC7_A13 & !_LC8_A13
         # !_LC6_A13 & !_LC7_A13 &  _LC8_A13;

-- Node name is '|CNT60:5|:14' = '|CNT60:5|ql2' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = DFFE( _EQ040,  _LC4_A15, GLOBAL( rst1),  VCC,  VCC);
  _EQ040 =  _LC2_A13 & !_LC6_A13 & !_LC7_A13
         #  _LC2_A13 & !_LC6_A13 & !_LC8_A13
         # !_LC2_A13 & !_LC6_A13 &  _LC7_A13 &  _LC8_A13;

-- Node name is '|CNT60:5|:13' = '|CNT60:5|ql3' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = DFFE( _EQ041,  _LC4_A15, GLOBAL( rst1),  VCC,  VCC);
  _EQ041 =  _LC3_A13 & !_LC8_A13
         #  _LC2_A13 & !_LC3_A13 &  _LC7_A13 &  _LC8_A13
         #  _LC2_A13 &  _LC3_A13 & !_LC7_A13
         # !_LC2_A13 &  _LC3_A13 &  _LC7_A13;

-- Node name is '|CNT60:5|:3' 
-- Equation name is '_LC4_C18', type is buried 
_LC4_C18 = DFFE( _EQ042,  _LC4_A15, GLOBAL( rst1),  VCC,  VCC);
  _EQ042 =  _LC3_A20 &  _LC6_A13
         #  _LC4_C18 & !_LC6_A13;

-- Node name is '|CNT60:5|:95' 
-- Equation name is '_LC6_A13', type is buried 
!_LC6_A13 = _LC6_A13~NOT;
_LC6_A13~NOT = LCELL( _EQ043);
  _EQ043 = !_LC3_A13
         # !_LC8_A13
         #  _LC2_A13
         #  _LC7_A13;

-- Node name is '|CNT60:5|~113~1' 
-- Equation name is '_LC1_A24', type is buried 
-- synthesized logic cell 
_LC1_A24 = LCELL( _EQ044);
  _EQ044 = !_LC3_A17 & !_LC3_A24 & !_LC4_A24 & !_LC8_A17;

-- Node name is '|CNT60:5|~113~2' 
-- Equation name is '_LC5_A13', type is buried 
-- synthesized logic cell 
_LC5_A13 = LCELL( _EQ045);
  _EQ045 = !_LC1_A15 & !_LC1_A20 & !_LC2_A13 & !_LC7_A13;

-- Node name is '|CNT60:5|~113~3' 
-- Equation name is '_LC1_A13', type is buried 
-- synthesized logic cell 
_LC1_A13 = LCELL( _EQ046);
  _EQ046 =  _LC2_A20 &  _LC3_A13 &  _LC4_A13 &  _LC8_A13;

-- Node name is '|CNT60:5|~113~4' 
-- Equation name is '_LC4_A17', type is buried 
-- synthesized logic cell 
_LC4_A17 = LCELL( _EQ047);
  _EQ047 =  _LC1_A17 &  _LC1_A24 &  _LC5_A13 &  _LC5_A17;

-- Node name is '|CNT60:5|:113' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ048);
  _EQ048 = !_LC1_A15 & !_LC1_A20 &  _LC2_A20 &  _LC4_A13;

-- Node name is '|SELECT2:100|:40' 
-- Equation name is '_LC3_C18', type is buried 
_LC3_C18 = LCELL( _EQ049);
  _EQ049 =  _LC4_C18 & !select2
         #  cp &  select2;

-- Node name is '|SELECT2:101|:40' 
-- Equation name is '_LC4_A15', type is buried 
_LC4_A15 = LCELL( _EQ050);
  _EQ050 =  _LC2_A15 & !select1
         #  cp &  select1;



Project Information               d:\11111111111111\max+plus\clock\clock60.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,124K