📄 clock60.rpt
字号:
- 1 - C 18 DFFE 0 1 1 2 |CNT24:36|ql0 (|CNT24:36|:16)
- 3 - C 23 DFFE 0 4 1 1 |CNT24:36|qh3 (|CNT24:36|:17)
- 4 - C 23 DFFE 0 4 1 2 |CNT24:36|qh2 (|CNT24:36|:18)
- 5 - C 23 DFFE 0 4 1 3 |CNT24:36|qh1 (|CNT24:36|:19)
- 7 - C 23 DFFE 0 3 1 4 |CNT24:36|qh0 (|CNT24:36|:20)
- 7 - C 18 OR2 ! 0 3 0 8 |CNT24:36|:95
- 2 - C 23 OR2 ! 0 4 0 5 |CNT24:36|:113
- 6 - A 17 AND2 0 2 0 1 |CNT60:2|LPM_ADD_SUB:140|addcore:adder|:55
- 7 - A 17 AND2 0 3 0 1 |CNT60:2|LPM_ADD_SUB:140|addcore:adder|:59
- 2 - A 15 DFFE + 0 2 0 1 |CNT60:2|:3
- 7 - A 24 DFFE + 0 3 1 3 |CNT60:2|ql3 (|CNT60:2|:13)
- 3 - A 24 DFFE + 0 3 1 3 |CNT60:2|ql2 (|CNT60:2|:14)
- 4 - A 24 DFFE + 0 2 1 4 |CNT60:2|ql1 (|CNT60:2|:15)
- 1 - B 12 DFFE + 0 0 1 5 |CNT60:2|ql0 (|CNT60:2|:16)
- 3 - A 17 DFFE + 0 3 1 2 |CNT60:2|qh3 (|CNT60:2|:17)
- 5 - A 17 DFFE + 0 3 1 4 |CNT60:2|qh2 (|CNT60:2|:18)
- 8 - A 17 DFFE + 0 3 1 4 |CNT60:2|qh1 (|CNT60:2|:19)
- 1 - A 17 DFFE + 0 1 1 6 |CNT60:2|qh0 (|CNT60:2|:20)
- 8 - A 24 OR2 ! 0 4 0 7 |CNT60:2|:95
- 2 - A 17 AND2 0 4 0 6 |CNT60:2|:113
- 4 - A 20 AND2 0 2 0 1 |CNT60:5|LPM_ADD_SUB:140|addcore:adder|:55
- 3 - A 15 AND2 0 3 0 1 |CNT60:5|LPM_ADD_SUB:140|addcore:adder|:59
- 4 - C 18 DFFE 0 3 0 1 |CNT60:5|:3
- 3 - A 13 DFFE 0 4 1 3 |CNT60:5|ql3 (|CNT60:5|:13)
- 2 - A 13 DFFE 0 4 1 3 |CNT60:5|ql2 (|CNT60:5|:14)
- 7 - A 13 DFFE 0 3 1 4 |CNT60:5|ql1 (|CNT60:5|:15)
- 8 - A 13 DFFE 0 1 1 6 |CNT60:5|ql0 (|CNT60:5|:16)
- 1 - A 15 DFFE 0 4 1 2 |CNT60:5|qh3 (|CNT60:5|:17)
- 2 - A 20 DFFE 0 4 1 4 |CNT60:5|qh2 (|CNT60:5|:18)
- 1 - A 20 DFFE 0 4 1 4 |CNT60:5|qh1 (|CNT60:5|:19)
- 4 - A 13 DFFE 0 2 1 6 |CNT60:5|qh0 (|CNT60:5|:20)
- 6 - A 13 OR2 ! 0 4 0 9 |CNT60:5|:95
- 1 - A 24 AND2 s 0 4 0 2 |CNT60:5|~113~1
- 5 - A 13 AND2 s 0 4 0 2 |CNT60:5|~113~2
- 1 - A 13 AND2 s 0 4 0 1 |CNT60:5|~113~3
- 4 - A 17 AND2 s 0 4 0 1 |CNT60:5|~113~4
- 3 - A 20 AND2 0 4 0 6 |CNT60:5|:113
- 3 - C 18 OR2 2 1 0 9 |SELECT2:100|:40
- 4 - A 15 OR2 2 1 0 9 |SELECT2:101|:40
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\11111111111111\max+plus\clock\clock60.rpt
clock60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 11/ 96( 11%) 0/ 48( 0%) 16/ 48( 33%) 1/16( 6%) 8/16( 50%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 10/ 48( 20%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\11111111111111\max+plus\clock\clock60.rpt
clock60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 cp
LCELL 9 |SELECT2:100|:40
LCELL 9 |SELECT2:101|:40
Device-Specific Information: d:\11111111111111\max+plus\clock\clock60.rpt
clock60
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 rst
INPUT 9 rst1
INPUT 9 rst2
Device-Specific Information: d:\11111111111111\max+plus\clock\clock60.rpt
clock60
** EQUATIONS **
cp : INPUT;
cp1024 : INPUT;
cp4096 : INPUT;
rst : INPUT;
rst1 : INPUT;
rst2 : INPUT;
select1 : INPUT;
select2 : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC6_A20;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC1_C23;
-- Node name is 'hou0'
-- Equation name is 'hou0', type is output
hou0 = _LC1_C18;
-- Node name is 'hou1'
-- Equation name is 'hou1', type is output
hou1 = _LC2_C18;
-- Node name is 'hou2'
-- Equation name is 'hou2', type is output
hou2 = _LC6_C18;
-- Node name is 'hou3'
-- Equation name is 'hou3', type is output
hou3 = _LC5_C18;
-- Node name is 'hou4'
-- Equation name is 'hou4', type is output
hou4 = _LC7_C23;
-- Node name is 'hou5'
-- Equation name is 'hou5', type is output
hou5 = _LC5_C23;
-- Node name is 'hou6'
-- Equation name is 'hou6', type is output
hou6 = _LC4_C23;
-- Node name is 'hou7'
-- Equation name is 'hou7', type is output
hou7 = _LC3_C23;
-- Node name is 'min0'
-- Equation name is 'min0', type is output
min0 = _LC8_A13;
-- Node name is 'min1'
-- Equation name is 'min1', type is output
min1 = _LC7_A13;
-- Node name is 'min2'
-- Equation name is 'min2', type is output
min2 = _LC2_A13;
-- Node name is 'min3'
-- Equation name is 'min3', type is output
min3 = _LC3_A13;
-- Node name is 'min4'
-- Equation name is 'min4', type is output
min4 = _LC4_A13;
-- Node name is 'min5'
-- Equation name is 'min5', type is output
min5 = _LC1_A20;
-- Node name is 'min6'
-- Equation name is 'min6', type is output
min6 = _LC2_A20;
-- Node name is 'min7'
-- Equation name is 'min7', type is output
min7 = _LC1_A15;
-- Node name is 'sec0'
-- Equation name is 'sec0', type is output
sec0 = _LC1_B12;
-- Node name is 'sec1'
-- Equation name is 'sec1', type is output
sec1 = _LC4_A24;
-- Node name is 'sec2'
-- Equation name is 'sec2', type is output
sec2 = _LC3_A24;
-- Node name is 'sec3'
-- Equation name is 'sec3', type is output
sec3 = _LC7_A24;
-- Node name is 'sec4'
-- Equation name is 'sec4', type is output
sec4 = _LC1_A17;
-- Node name is 'sec5'
-- Equation name is 'sec5', type is output
sec5 = _LC8_A17;
-- Node name is 'sec6'
-- Equation name is 'sec6', type is output
sec6 = _LC5_A17;
-- Node name is 'sec7'
-- Equation name is 'sec7', type is output
sec7 = _LC3_A17;
-- Node name is '|ALARM:94|~416~1'
-- Equation name is '_LC5_A24', type is buried
-- synthesized logic cell
_LC5_A24 = LCELL( _EQ001);
_EQ001 = cp4096 & !_LC1_A17 & !_LC5_A17 & !_LC7_A24;
-- Node name is '|ALARM:94|~416~2'
-- Equation name is '_LC6_A24', type is buried
-- synthesized logic cell
_LC6_A24 = LCELL( _EQ002);
_EQ002 = !_LC3_A13 & !_LC4_A13 & _LC5_A24 & !_LC8_A13;
-- Node name is '|ALARM:94|~416~3'
-- Equation name is '_LC2_A24', type is buried
-- synthesized logic cell
_LC2_A24 = LCELL( _EQ003);
_EQ003 = _LC1_A24 & !_LC2_A20 & _LC5_A13 & _LC6_A24;
-- Node name is '|ALARM:94|~416~4'
-- Equation name is '_LC5_A20', type is buried
-- synthesized logic cell
_LC5_A20 = LCELL( _EQ004);
_EQ004 = _LC2_A24 & !_LC3_A20
# _LC2_A24 & !_LC6_A13
# !_LC2_A17 & _LC2_A24;
-- Node name is '|ALARM:94|~416~5'
-- Equation name is '_LC7_A20', type is buried
-- synthesized logic cell
!_LC7_A20 = _LC7_A20~NOT;
_LC7_A20~NOT = LCELL( _EQ005);
_EQ005 = _LC2_A17 & _LC3_A20 & _LC6_A13;
-- Node name is '|ALARM:94|~416~6'
-- Equation name is '_LC8_A20', type is buried
-- synthesized logic cell
_LC8_A20 = LCELL( _EQ006);
_EQ006 = !_LC7_A20 & !_LC7_A24
# _LC1_A13 & _LC4_A17 & _LC7_A24;
-- Node name is '|ALARM:94|:416'
-- Equation name is '_LC6_A20', type is buried
_LC6_A20 = LCELL( _EQ007);
_EQ007 = !_LC1_B12 & _LC5_A20
# cp1024 & !_LC1_B12 & _LC8_A20;
-- Node name is '|CNT24:36|LPM_ADD_SUB:140|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C23', type is buried
_LC6_C23 = LCELL( _EQ008);
_EQ008 = _LC5_C23 & _LC7_C23;
-- Node name is '|CNT24:36|LPM_ADD_SUB:140|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C23', type is buried
_LC8_C23 = LCELL( _EQ009);
_EQ009 = _LC4_C23 & _LC5_C23 & _LC7_C23;
-- Node name is '|CNT24:36|LPM_ADD_SUB:208|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C18', type is buried
!_LC8_C18 = _LC8_C18~NOT;
_LC8_C18~NOT = LCELL( _EQ010);
_EQ010 = !_LC2_C18
# !_LC1_C18;
-- Node name is '|CNT24:36|:20' = '|CNT24:36|qh0'
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = DFFE( _EQ011, _LC3_C18, GLOBAL( rst2), VCC, VCC);
_EQ011 = !_LC7_C18 & _LC7_C23
# !_LC2_C23 & _LC7_C18 & !_LC7_C23;
-- Node name is '|CNT24:36|:19' = '|CNT24:36|qh1'
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = DFFE( _EQ012, _LC3_C18, GLOBAL( rst2), VCC, VCC);
_EQ012 = _LC5_C23 & !_LC7_C18
# !_LC2_C23 & _LC5_C23 & !_LC7_C23
# !_LC2_C23 & !_LC5_C23 & _LC7_C18 & _LC7_C23;
-- Node name is '|CNT24:36|:18' = '|CNT24:36|qh2'
-- Equation name is '_LC4_C23', type is buried
_LC4_C23 = DFFE( _EQ013, _LC3_C18, GLOBAL( rst2), VCC, VCC);
_EQ013 = !_LC2_C23 & _LC4_C23 & !_LC6_C23
# !_LC2_C23 & !_LC4_C23 & _LC6_C23 & _LC7_C18
# _LC4_C23 & !_LC7_C18;
-- Node name is '|CNT24:36|:17' = '|CNT24:36|qh3'
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = DFFE( _EQ014, _LC3_C18, GLOBAL( rst2), VCC, VCC);
_EQ014 = _LC3_C23 & !_LC7_C18
# !_LC2_C23 & _LC3_C23 & !_LC8_C23
# !_LC2_C23 & !_LC3_C23 & _LC7_C18 & _LC8_C23;
-- Node name is '|CNT24:36|:16' = '|CNT24:36|ql0'
-- Equation name is '_LC1_C18', type is buried
_LC1_C18 = DFFE(!_LC1_C18, _LC3_C18, GLOBAL( rst2), VCC, VCC);
-- Node name is '|CNT24:36|:15' = '|CNT24:36|ql1'
-- Equation name is '_LC2_C18', type is buried
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