📄 clock60.rpt
字号:
Project Information d:\11111111111111\max+plus\clock\clock60.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/06/2008 11:27:49
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
clock60 EPF10K10LC84-3 8 26 0 0 0 % 53 9 %
User Pins: 8 26 0
Project Information d:\11111111111111\max+plus\clock\clock60.rpt
** FILE HIERARCHY **
|cnt60:5|
|cnt60:5|lpm_add_sub:140|
|cnt60:5|lpm_add_sub:140|addcore:adder|
|cnt60:5|lpm_add_sub:140|altshift:result_ext_latency_ffs|
|cnt60:5|lpm_add_sub:140|altshift:carry_ext_latency_ffs|
|cnt60:5|lpm_add_sub:140|altshift:oflow_ext_latency_ffs|
|cnt60:5|lpm_add_sub:208|
|cnt60:5|lpm_add_sub:208|addcore:adder|
|cnt60:5|lpm_add_sub:208|altshift:result_ext_latency_ffs|
|cnt60:5|lpm_add_sub:208|altshift:carry_ext_latency_ffs|
|cnt60:5|lpm_add_sub:208|altshift:oflow_ext_latency_ffs|
|cnt60:2|
|cnt60:2|lpm_add_sub:140|
|cnt60:2|lpm_add_sub:140|addcore:adder|
|cnt60:2|lpm_add_sub:140|altshift:result_ext_latency_ffs|
|cnt60:2|lpm_add_sub:140|altshift:carry_ext_latency_ffs|
|cnt60:2|lpm_add_sub:140|altshift:oflow_ext_latency_ffs|
|cnt60:2|lpm_add_sub:208|
|cnt60:2|lpm_add_sub:208|addcore:adder|
|cnt60:2|lpm_add_sub:208|altshift:result_ext_latency_ffs|
|cnt60:2|lpm_add_sub:208|altshift:carry_ext_latency_ffs|
|cnt60:2|lpm_add_sub:208|altshift:oflow_ext_latency_ffs|
|cnt24:36|
|cnt24:36|lpm_add_sub:140|
|cnt24:36|lpm_add_sub:140|addcore:adder|
|cnt24:36|lpm_add_sub:140|altshift:result_ext_latency_ffs|
|cnt24:36|lpm_add_sub:140|altshift:carry_ext_latency_ffs|
|cnt24:36|lpm_add_sub:140|altshift:oflow_ext_latency_ffs|
|cnt24:36|lpm_add_sub:208|
|cnt24:36|lpm_add_sub:208|addcore:adder|
|cnt24:36|lpm_add_sub:208|altshift:result_ext_latency_ffs|
|cnt24:36|lpm_add_sub:208|altshift:carry_ext_latency_ffs|
|cnt24:36|lpm_add_sub:208|altshift:oflow_ext_latency_ffs|
|alarm:94|
|select2:100|
|select2:101|
Device-Specific Information: d:\11111111111111\max+plus\clock\clock60.rpt
clock60
***** Logic for device 'clock60' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R R R R R R O
E E E E E E E s E E E N
S S S S S S S V e S G S S F
E E E E E E E C l E N E E _ ^
R R R R R R R C s e R D R s s R # D n
V V V V V V V I e r c V I V e e V T O C
E E E E E E E N c s c t E N E c c E C N E
D D D D D D D T 0 t p 1 D T D 1 2 D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | sec4
^nCE | 14 72 | min3
#TDI | 15 71 | min4
min5 | 16 70 | sec6
min6 | 17 69 | min0
cp4096 | 18 68 | GNDINT
sec3 | 19 67 | RESERVED
VCCINT | 20 66 | RESERVED
RESERVED | 21 65 | RESERVED
min2 | 22 EPF10K10LC84-3 64 | RESERVED
RESERVED | 23 63 | VCCINT
RESERVED | 24 62 | co
RESERVED | 25 61 | hou1
GNDINT | 26 60 | hou6
hou0 | 27 59 | hou5
hou7 | 28 58 | hou4
hou3 | 29 57 | #TMS
hou2 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G r s r V G m m c s s a R
C n E E E E E C N s e s C N i i p e e l E
C C S S S S S C D t l t C D n n 1 c c a S
I O E E E E E I I 1 e 2 I I 1 7 0 7 5 r E
N N R R R R R N N c N N 2 m R
T F V V V V V T T t T T 4 V
I E E E E E 2 E
G D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\11111111111111\max+plus\clock\clock60.rpt
clock60
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A13 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
A15 4/ 8( 50%) 2/ 8( 25%) 2/ 8( 25%) 2/2 2/2 9/22( 40%)
A17 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 1/2 3/22( 13%)
A20 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
A24 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
B12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 0/22( 0%)
C18 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 2/2 5/22( 22%)
C23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 28/53 ( 52%)
Total logic cells used: 53/576 ( 9%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.32/4 ( 83%)
Total fan-in: 176/2304 ( 7%)
Total input pins required: 8
Total input I/O cell registers required: 0
Total output pins required: 26
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 53
Total flipflops required: 27
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 10/ 576 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 4 0 8 0 0 8 0 0 0 8 36/0
B: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 8 0 16/0
Total: 0 0 0 0 0 0 0 0 0 0 0 1 0 8 0 4 0 8 8 0 8 0 0 8 8 53/0
Device-Specific Information: d:\11111111111111\max+plus\clock\clock60.rpt
clock60
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 2 cp
49 - - - 16 INPUT 0 0 0 1 cp1024
18 - - A -- INPUT 0 0 0 1 cp4096
2 - - - -- INPUT G 0 0 0 0 rst
42 - - - -- INPUT G 0 0 0 0 rst1
44 - - - -- INPUT G 0 0 0 0 rst2
84 - - - -- INPUT 0 0 0 1 select1
43 - - - -- INPUT 0 0 0 1 select2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\11111111111111\max+plus\clock\clock60.rpt
clock60
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
52 - - - 19 OUTPUT 0 1 0 0 alarm
62 - - C -- OUTPUT 0 1 0 0 co
27 - - C -- OUTPUT 0 1 0 0 hou0
61 - - C -- OUTPUT 0 1 0 0 hou1
30 - - C -- OUTPUT 0 1 0 0 hou2
29 - - C -- OUTPUT 0 1 0 0 hou3
58 - - C -- OUTPUT 0 1 0 0 hou4
59 - - C -- OUTPUT 0 1 0 0 hou5
60 - - C -- OUTPUT 0 1 0 0 hou6
28 - - C -- OUTPUT 0 1 0 0 hou7
69 - - A -- OUTPUT 0 1 0 0 min0
47 - - - 14 OUTPUT 0 1 0 0 min1
22 - - B -- OUTPUT 0 1 0 0 min2
72 - - A -- OUTPUT 0 1 0 0 min3
71 - - A -- OUTPUT 0 1 0 0 min4
16 - - A -- OUTPUT 0 1 0 0 min5
17 - - A -- OUTPUT 0 1 0 0 min6
48 - - - 15 OUTPUT 0 1 0 0 min7
3 - - - 12 OUTPUT 0 1 0 0 sec0
80 - - - 23 OUTPUT 0 1 0 0 sec1
79 - - - 24 OUTPUT 0 1 0 0 sec2
19 - - A -- OUTPUT 0 1 0 0 sec3
73 - - A -- OUTPUT 0 1 0 0 sec4
51 - - - 18 OUTPUT 0 1 0 0 sec5
70 - - A -- OUTPUT 0 1 0 0 sec6
50 - - - 17 OUTPUT 0 1 0 0 sec7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\11111111111111\max+plus\clock\clock60.rpt
clock60
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 24 AND2 s 1 3 0 1 |ALARM:94|~416~1
- 6 - A 24 AND2 s 0 4 0 1 |ALARM:94|~416~2
- 2 - A 24 AND2 s 0 4 0 1 |ALARM:94|~416~3
- 5 - A 20 OR2 s 0 4 0 1 |ALARM:94|~416~4
- 7 - A 20 AND2 s ! 0 3 0 1 |ALARM:94|~416~5
- 8 - A 20 OR2 s 0 4 0 1 |ALARM:94|~416~6
- 6 - A 20 OR2 1 3 1 0 |ALARM:94|:416
- 6 - C 23 AND2 0 2 0 1 |CNT24:36|LPM_ADD_SUB:140|addcore:adder|:55
- 8 - C 23 AND2 0 3 0 1 |CNT24:36|LPM_ADD_SUB:140|addcore:adder|:59
- 8 - C 18 OR2 ! 0 2 0 3 |CNT24:36|LPM_ADD_SUB:208|addcore:adder|:55
- 1 - C 23 DFFE 0 3 1 0 |CNT24:36|:3
- 5 - C 18 DFFE 0 4 1 1 |CNT24:36|ql3 (|CNT24:36|:13)
- 6 - C 18 DFFE 0 3 1 2 |CNT24:36|ql2 (|CNT24:36|:14)
- 2 - C 18 DFFE 0 3 1 1 |CNT24:36|ql1 (|CNT24:36|:15)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -