📄 cnt60.rpt
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Device-Specific Information: e:\11111111111111\max+plus\clock\cnt60.rpt
cnt60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 5/ 96( 5%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\11111111111111\max+plus\clock\cnt60.rpt
cnt60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: e:\11111111111111\max+plus\clock\cnt60.rpt
cnt60
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 rst
Device-Specific Information: e:\11111111111111\max+plus\clock\cnt60.rpt
cnt60
** EQUATIONS **
clk : INPUT;
rst : INPUT;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC4_B4;
-- Node name is ':20' = 'qh0'
-- Equation name is 'qh0', location is LC8_B7, type is buried.
qh0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ001 = !_LC7_B7 & qh0
# _LC7_B7 & !qh0;
-- Node name is ':19' = 'qh1'
-- Equation name is 'qh1', location is LC3_B7, type is buried.
qh1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ002 = !_LC2_B7 & !qh0 & qh1
# !_LC2_B7 & _LC7_B7 & qh0 & !qh1
# !_LC7_B7 & qh1;
-- Node name is ':18' = 'qh2'
-- Equation name is 'qh2', location is LC6_B4, type is buried.
qh2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ003 = _LC2_B4 & !_LC2_B7 & _LC7_B7
# !_LC7_B7 & qh2;
-- Node name is ':17' = 'qh3'
-- Equation name is 'qh3', location is LC1_B4, type is buried.
qh3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ004 = !_LC2_B7 & !_LC3_B4 & qh3
# !_LC2_B7 & _LC3_B4 & _LC7_B7 & !qh3
# !_LC7_B7 & qh3;
-- Node name is ':16' = 'ql0'
-- Equation name is 'ql0', location is LC4_B7, type is buried.
ql0 = DFFE(!ql0, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
-- Node name is ':15' = 'ql1'
-- Equation name is 'ql1', location is LC1_B7, type is buried.
ql1 = DFFE( _EQ005, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ005 = !_LC7_B7 & !ql0 & ql1
# !_LC7_B7 & ql0 & !ql1;
-- Node name is ':14' = 'ql2'
-- Equation name is 'ql2', location is LC6_B7, type is buried.
ql2 = DFFE( _EQ006, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ006 = !_LC7_B7 & !ql1 & ql2
# !_LC7_B7 & !ql0 & ql2
# !_LC7_B7 & ql0 & ql1 & !ql2;
-- Node name is ':13' = 'ql3'
-- Equation name is 'ql3', location is LC5_B7, type is buried.
ql3 = DFFE( _EQ007, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ007 = !ql0 & ql3
# ql0 & ql1 & ql2 & !ql3
# !ql1 & ql2 & ql3
# ql1 & !ql2 & ql3;
-- Node name is 'qout0'
-- Equation name is 'qout0', type is output
qout0 = ql0;
-- Node name is 'qout1'
-- Equation name is 'qout1', type is output
qout1 = ql1;
-- Node name is 'qout2'
-- Equation name is 'qout2', type is output
qout2 = ql2;
-- Node name is 'qout3'
-- Equation name is 'qout3', type is output
qout3 = ql3;
-- Node name is 'qout4'
-- Equation name is 'qout4', type is output
qout4 = qh0;
-- Node name is 'qout5'
-- Equation name is 'qout5', type is output
qout5 = qh1;
-- Node name is 'qout6'
-- Equation name is 'qout6', type is output
qout6 = qh2;
-- Node name is 'qout7'
-- Equation name is 'qout7', type is output
qout7 = qh3;
-- Node name is '|LPM_ADD_SUB:140|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = LCELL( _EQ008);
_EQ008 = qh0 & qh1 & qh2;
-- Node name is '|LPM_ADD_SUB:140|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = LCELL( _EQ009);
_EQ009 = !qh1 & qh2
# !qh0 & qh2
# qh0 & qh1 & !qh2;
-- Node name is ':3'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = DFFE( _EQ010, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ010 = _LC2_B7 & _LC7_B7
# _LC4_B4 & !_LC7_B7;
-- Node name is ':95'
-- Equation name is '_LC7_B7', type is buried
!_LC7_B7 = _LC7_B7~NOT;
_LC7_B7~NOT = LCELL( _EQ011);
_EQ011 = ql1
# !ql3
# ql2
# !ql0;
-- Node name is ':113'
-- Equation name is '_LC2_B7', type is buried
!_LC2_B7 = _LC2_B7~NOT;
_LC2_B7~NOT = LCELL( _EQ012);
_EQ012 = !qh2
# qh1
# qh3
# !qh0;
Project Information e:\11111111111111\max+plus\clock\cnt60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,049K
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