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<title>SignalCompiler report D:\my_eda3\DDS\dds_top_DspBuilder_Report.html</title>
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<h3> SignalCompiler report </h3>
<i><h5>Use the right-click mouse button to naviguate through dds_top_DspBuilder_Report.html
</h5></i><hr><h3>Project Setting</h3><TABLE>
<TR>
<TD><b>Model</b> </TD> <TD> dds_top</TD>
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<TR>
<TD><b>Directory</b> </TD> <TD> D:\my_eda3\DDS</TD>
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<TD><b>Device family</b> </TD> <TD>STRATIX</TD>
</TR>
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<TD><b>Synthesis tool</b> </TD> <TD>Quartus II</TD>
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<TD> <b>Optimization </b></TD> <TD>Balanced</TD>
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<TD> <b>Date</b> </TD> <TD>Saturday, May 05, 2007</TD>
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<TD> <b>Time</b> </TD> <TD>16:59:57</TD>
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<TD><b>Version</b> </TD> <TD> 7.0 Build 33</TD>
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<hr>
<h3>Compilation status</h3>
<TABLE>
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<TD>Convert Mdl to VHDL </TD> <TD><b>:</b> PASSED </TD><TD></TD>
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<TD>Synthesis </TD> <TD><b>:</b> PASSED </TD><TD><A HREF="dds_top.map.rpt" >dds_top.map.rpt </A></TD>
</TR>
<TR> <TD>Quartus II Fitter</TD> <TD><b>:</b> --------- </TD><TD></TD></TR>
</TABLE>
<hr>
<!--<h3>Resource Usage Summary</h3>-->
<h3>Resource Utilization</h3>
<TABLE>
<TR><TD>Analysis & Synthesis Status</TD><TD>Successful - Sat May 05 17:01:00 2007</TR></TR>
<TR><TD>Quartus II Version</TD><TD>7.0 Build 33 02/05/2007 SJ Full Version</TR></TR>
<TR><TD>Revision Name</TD><TD>dds_top</TR></TR>
<TR><TD>Top-level Entity Name</TD><TD>dds_top</TR></TR>
<TR><TD>Family</TD><TD>Stratix</TR></TR>
<TR><TD>Total logic elements</TD><TD>126</TR></TR>
<TR><TD>Total pins</TD><TD>62</TR></TR>
<TR><TD>Total virtual pins</TD><TD>0</TR></TR>
<TR><TD>Total memory bits</TD><TD>10,240</TR></TR>
<TR><TD>DSP block 9-bit elements</TD><TD>2</TR></TR>
<TR><TD>Total PLLs</TD><TD>0</TR></TR>
<TR><TD>Total DLLs</TD><TD>0</TR></TR>
</TABLE>
<hr>
<!--<h3>Timing Analyzer Summary</h3>-->
<h3>Pin-Out</h3><TABLE>
<TR><TD><b>Pin name </b></TD>
<TD><b>Pin Direction </b></TD>
<TD><b>Bus Type </b></TD></TR>
<TR><TD> clock </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> sclrp </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> Aword </TD><TD> in </TD><TD>std_logic_vector(9 downto 0)</TD></TR><TR><TD> Fword </TD><TD> in </TD><TD>std_logic_vector(31 downto 0)</TD></TR><TR><TD> Pword </TD><TD> in </TD><TD>std_logic_vector(7 downto 0)</TD></TR><TR><TD> Sout </TD><TD> </TD><TD> out </TD><TD>std_logic_vector(9 downto 0) )</TD></TR><TR><TD></TR></TABLE><br>
<p><b>Clock input pin (clock):</b>
All registered blocks use the input clock signal <b>'clock'</b>. dds_top.mdl does not use PLL.<br><b>Reset input pin (sclrp):</b>
All registered blocks use the global reset input signal <b>'sclrp'</b> , which is synchronous and active high</p><hr>
<h3>Files generated by SignalCompiler</h3><TABLE BORDER>
<TR>
<TD> <b>dds_top.vhd</b> </TD><TD>VHDL representation of the design for synthesis and simulation </TD>
</TR>
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<TD> <b>DDS.vhd</b> </TD><TD>VHDL hierarchy for synthesis and simulation </TD>
</TR>
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</TR>
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<TD> <b>dds_top_quartus.tcl</b> </TD><TD>Tcl script for Quartus<font size="-1"><sup>®</font></sup> II compilation. <p><I>When compiling the design manually in the Quartus II software, type </i><b>source dds_top_quartus.tcl </b><i> in the Quartus II tcl console (Auxiliary Windows). The Quartus II software executes the Tcl script that sets up the project and environment for your design.</I></p></TD>
</TR>
<TR>
<TD> <b>dds_top.vec</b> </TD><TD>Quartus<font size="-1"><sup>®</font></sup> II simulation vector file </TD>
</TR>
<TR>
<TD> <b>dds_top.bsf</b> </TD><TD>Quartus<font size="-1"><sup>®</font></sup> II symbol file</TD>
</TR>
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<TD><b> tb_dds_top.vhd</b> </TD><TD>VHDL design testbench for simulation </TD>
</TR>
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<TD> <b>tb_dds_top.tcl</b> </TD><TD>Tcl script for ModelSim simulation <p><I>type </i><b>do tb_dds_top.tcl </b><i> at Modelsim prompt.</p></TD>
</TR>
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<TD><b> tb_dds_top.v</b> </TD><TD>Verilog design testbench for simulation with Quartus II Verilog Output File (.vo)</TD>
</TR>
</TABLE><br>
<hr>
<h3>Synthesis & compilation log files</h3>
<!--<p><A HREF="dds_top.srr">Synplicity Log</A></p>-->
<!--<p><A HREF="exemplar.log">Leonardo Log</A></p>-->
<p><A HREF="dds_top.map.rpt" >Quartus II Map Log</A></p>
<!--<p><A HREF="dds_top.fit.rpt">Quartus II Fit Log</A></p>-->
<hr>
<h3>Entity dds_top</h3>
<p><A HREF="DSPBuilder_dds_top\dds_topblockInfos.html">Information page</A> on the DSP Builder blocks used in dds_top.</p>
<h4>Hierarchy information</h4>
<p>
This section lists the "Hdl Sub-System" block used in the design (Black Box and VHDL)
with the number of instance of those blocks accross the hierarchy branches.
</p>
<TABLE>
<TR>
<TD><a href="#DDS"> DDS <a></TD> <TD> 1 </TD>
</TR>
</TABLE>
<p><i>VHDL SubSystem </i> :
Each "Hdl Sub-System" map to a unique VHDL entity generated on-the-fly by SignalCompiler, and therefore must
be uniquified in Simulink.
Make sure that "Hdl Sub-System" block with identical names have the
exact same functionality
</p><p><i>Black Box SubSystem</i> :
A Black Box SubSystem is used to import VHDL design into the design using the HDL SubSystem mechanism. SignalCompiler generates only the black component declaration and mapping. For clock signals, SignalCompiler will connect automatically to the global "clock" signal of the design the signal of the black box which has the instance name "simulink_clock"</p>
<h4>Bus width extension</h4><p> In order to maintain bit accuracy between the Simulink domain and the VHDL domain, the MDL to VHDL conversion process may extend or reduce bus width. This occurs <table><tr><td>- When the block input port bit width is greater than the signal input port bit width, SignalCompiler sign extends the signal bit width to the input port bit width.</td></tr><tr><td>- When the block input port bit width is smaller than the signal input port bit width, SignalCompiler truncates the signal bit width to the input port bit width.</td></tr><tr><td>- For designs in which unsigned integer signals are used in Simulink, SignalCompiler translates the Simulink unsigned bus type with width w into a VHDL signed bus of width w + 1 where the MSB bit is stuck to 0.</td></tr></table></p><pre> "DDS" : input port "Pword" [8].[0] is driven by a signal [9].[0].
"DDS" : input port "Fword" [32].[0] is driven by a signal [33].[0].
"DDS" : input port "Aword" [10].[0] is driven by a signal [11].[0].
</pre><h4>Warning Section</h4><hr>
<a name="DDS"> </a>
<h3>Entity DDS</h3>
<p><A HREF="DSPBuilder_dds_top\DDSblockInfos.html">Information page</A> on the DSP Builder blocks used in DDS.</p>
<hr>
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<TD> </TD><TD align="right"> <A HREF="E:\altera\70\DSPBuilder\Altlib\..\doc\ug_dspbuilderTOC.html">help</A></TD>
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DSP Builder <br>Quartus II development tool and MATLAB/Simulink Interface
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