dds_topaltblk.xml

DDS的频率转换可以以近似认为是即时的

<dds_top>
<dspbuilder_info>
	<dspbuilder_version>7.0</dspbuilder_version>
	<dspbuilder_build_number>Build 33</dspbuilder_build_number>
	<dspbuilder_build_date>02/05/2007</dspbuilder_build_date>
	<toplevel_design_name>dds_top</toplevel_design_name>
	<date_stamp>20070505165701</date_stamp>
</dspbuilder_info>
   <block_dspbuilder>
      <db_block>
         <instancename>Aword</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>1</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>sgn</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>InputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>10</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>3</dstport>
            <dstblk>DDS</dstblk>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>Fword</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>2</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>sgn</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>InputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>32</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>2</dstport>
            <dstblk>DDS</dstblk>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>Pword</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>3</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>sgn</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>InputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>8</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>DDS</dstblk>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>Sout</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>4</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>sgn</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>OutputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>10</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>DDS</srcblk>
            <srcport>1</srcport>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>DDS</instancename>
         <sourcename>SubSystemAlteraBlockSet</sourcename>
         <instancenumber>5</instancenumber>
         <inport>3</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Pword</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Fword</srcblk>
            <srcport>1</srcport>
            <inportpos>3</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Aword</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>Sout</dstblk>
         </port_db>
         <nparameter>1</nparameter>
      </db_block>
   </block_dspbuilder>
<top_sources>
	<library></library>
</top_sources>
   <top_subsystem>
      <design_subsystem>DDS</design_subsystem>
   </top_subsystem>
   <top_parameters>
      <starttime>0.0</starttime>
      <stoptime>5000</stoptime>
      <fixedstep>auto</fixedstep>
      <nsubsystem>1</nsubsystem>
      <nblocks>5</nblocks>
   </top_parameters>
   <top_signalcompiler>
      <family>Stratix</family>
      <opt>Balanced</opt>
      <synthtool>Others</synthtool>
      <vstim>on</vstim>
      <SynthAct>None</SynthAct>
      <workdir>D:\my_eda3\DDS</workdir>
      <Procetype>prod</Procetype>
      <UseReset>on</UseReset>
      <ResetPin>Active High</ResetPin>
      <ClockPin>Output to Pin</ClockPin>
      <ClockPeriod>20</ClockPeriod>
      <UseSignalTap>off</UseSignalTap>
      <CreatePtfFile>off</CreatePtfFile>
      <SignalTapDepth>128</SignalTapDepth>
      <VerilogSupport>off</VerilogSupport>
      <JTAGCable>USB-Blaster [USB-0]</JTAGCable>
      <bContainMegaCoreIpTb>0</bContainMegaCoreIpTb>
   </top_signalcompiler>
</dds_top>