ddsaltblk.xml

DDS的频率转换可以以近似认为是即时的

            <pvalue>off</pvalue>
            <pname>direction</pname>
            <pvalue>+</pvalue>
            <pname>Inputs</pname>
            <pvalue>2</pvalue>
            <pname>MaskValue</pname>
            <pvalue>1</pvalue>
            <pname>pipeline</pname>
            <pvalue>on</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>AltBus</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Delay</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>AltBus</dstblk>
         </port_db>
         <nparameter>6</nparameter>
      </db_block>
      <db_block>
         <instancename>ParallelAdderSubtractor1</instancename>
         <sourcename>SumAlteraBlockSet</sourcename>
         <instancenumber>9</instancenumber>
         <inport>2</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>clken</pname>
            <pvalue>off</pvalue>
            <pname>direction</pname>
            <pvalue>+</pvalue>
            <pname>Inputs</pname>
            <pvalue>2</pvalue>
            <pname>MaskValue</pname>
            <pvalue>1</pvalue>
            <pname>pipeline</pname>
            <pvalue>on</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Pword</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>BusConversion</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>LUT</dstblk>
         </port_db>
         <nparameter>6</nparameter>
      </db_block>
      <db_block>
         <instancename>LUT</instancename>
         <sourcename>LUTAlteraBlockSet</sourcename>
         <instancenumber>10</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>BusType</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>10</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>bwaddr</pname>
            <pvalue>10</pvalue>
            <pname>lpm</pname>
            <pvalue>off</pvalue>
            <pname>pipeline</pname>
            <pvalue>off</pvalue>
            <pname>clken</pname>
            <pvalue>off</pvalue>
            <pname>LocPin</pname>
            <pvalue>ddsDDSLUT</pvalue>
            <pname>ena</pname>
            <pvalue>off</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>ParallelAdderSubtractor1</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>Product</dstblk>
         </port_db>
         <nparameter>10</nparameter>
      </db_block>
      <db_block>
         <instancename>BusConversion</instancename>
         <sourcename>SubBusAlteraBlockSet</sourcename>
         <instancenumber>11</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>BusType</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>Outputs</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>32</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>obwl</pname>
            <pvalue>10</pvalue>
            <pname>obwr</pname>
            <pvalue>0</pvalue>
            <pname>lsb</pname>
            <pvalue>22</pvalue>
            <pname>msb</pname>
            <pvalue>31</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>AltBus</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>2</dstport>
            <dstblk>ParallelAdderSubtractor1</dstblk>
         </port_db>
         <nparameter>11</nparameter>
      </db_block>
      <db_block>
         <instancename>BusConversion1</instancename>
         <sourcename>SubBusAlteraBlockSet</sourcename>
         <instancenumber>12</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>BusType</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>Outputs</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>20</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>obwl</pname>
            <pvalue>10</pvalue>
            <pname>obwr</pname>
            <pvalue>0</pvalue>
            <pname>lsb</pname>
            <pvalue>9</pvalue>
            <pname>msb</pname>
            <pvalue>18</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Product</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>Sout</dstblk>
         </port_db>
         <nparameter>11</nparameter>
      </db_block>
   </block_dspbuilder>
   <hierarchy_parameters BlackBox="0">
      <nBlock>12</nBlock>
   </hierarchy_parameters>
   <hierarchy_port>
      <hierarchy_inport>
         <inportvalue>1</inportvalue>
         <inportname>Pword</inportname>
         <inportbtype>UnsignedInteger</inportbtype>
         <inportbwl>10</inportbwl>
         <inportbwr>0</inportbwr>
      </hierarchy_inport>
      <hierarchy_inport>
         <inportvalue>2</inportvalue>
         <inportname>Fword</inportname>
         <inportbtype>UnsignedInteger</inportbtype>
         <inportbwl>32</inportbwl>
         <inportbwr>0</inportbwr>
      </hierarchy_inport>
      <hierarchy_inport>
         <inportvalue>3</inportvalue>
         <inportname>Aword</inportname>
         <inportbtype>UnsignedInteger</inportbtype>
         <inportbwl>10</inportbwl>
         <inportbwr>0</inportbwr>
      </hierarchy_inport>
      <hierarchy_outport>
         <outportvalue>1</outportvalue>
         <outportname>Sout</outportname>
         <outportbtype>UnsignedInteger</outportbtype>
         <outportbwl>10</outportbwl>
         <outportbwr>0</outportbwr>
      </hierarchy_outport>
   </hierarchy_port>
<top_sources>
	<library></library>
</top_sources>
</DDS>
   <top_subsystem>
      <design_subsystem>DDS</design_subsystem>
   </top_subsystem>
   <top_parameters>
      <starttime>0.0</starttime>
      <stoptime>5000</stoptime>
      <fixedstep>auto</fixedstep>
      <nsubsystem>1</nsubsystem>
      <nblocks>12</nblocks>
   </top_parameters>
   <top_signalcompiler>
      <family>Stratix</family>
      <opt>Balanced</opt>
      <synthtool>Others</synthtool>
      <vstim>on</vstim>
      <SynthAct>None</SynthAct>
      <workdir>D:\my_eda3\DDS</workdir>
      <Procetype>prod</Procetype>
      <UseReset>on</UseReset>
      <ResetPin>Active High</ResetPin>
      <ClockPin>Output to Pin</ClockPin>
      <ClockPeriod>20</ClockPeriod>
      <UseSignalTap>off</UseSignalTap>
      <CreatePtfFile>off</CreatePtfFile>
      <SignalTapDepth>128</SignalTapDepth>
      <VerilogSupport>off</VerilogSupport>
      <JTAGCable>USB-Blaster [USB-0]</JTAGCable>
      <bContainMegaCoreIpTb>0</bContainMegaCoreIpTb>
   </top_signalcompiler>
</dds>