uart_send.vhd

来自「256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串」· VHDL 代码 · 共 109 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity uart_send is
    Port (clk           :in std_logic;
	  reset         :in std_logic;
	  wenb          :in std_logic;
	  status      :out std_logic;
	  din           :in std_logic_vector(7 downto 0);
	  txd           :out std_logic
           );
end uart_send;

architecture Behavioral of uart_send is

 signal din_s      :std_logic_vector(7 downto 0);
 signal count_in   :std_logic_vector(8 downto 0);
 signal txd_s      :std_logic;
 signal txd_f      :std_logic;
 signal clr,clr_in :std_logic;
 signal clr_in1    :std_logic;
 signal clr_in2    :std_logic;
-- signal wenb1,wenb2,wenb3:std_logic;

begin

process(reset,wenb,clr)
begin
    if (reset='1' or clr='1') then
       din_s <= (others=>'0');
       txd_f <= '0';
    elsif (wenb'event and wenb='1') then
       din_s <= din;
       txd_f <='1';
    end if;
end process;

process(reset,clk,clr)

variable count      :integer range 0 to 360;

begin
    if (reset='1' or clr = '1') then
        count := 0;
	clr_in <= '0';
    elsif (clk'event and clk='1') then
	if (txd_f='1') then
	    if (count_in(4 downto 0)="11000") then
               count := count + 8;
	       else count := count + 1;
	    end if;
            if (count=352) then
	       clr_in <= '1';
	       count := 0;
	    end if;
	end if;
	count_in<=conv_std_logic_vector(count,9);
    end if;
end process;

    status <= not(txd_f);

process(clk)
begin
    if (clk'event and clk='1') then
	clr_in1 <= clr_in;
    end if;
end process;

process(clk)
begin
    if (clk'event and clk='0') then
	clr_in2 <= clr_in1;
    end if;
end process;
       
     clr <= clr_in1 and not(clr_in2);

process(count_in(8 downto 5),din_s)
begin
    case count_in(8 downto 5) is
	when "0001" => txd_s <= '0';
	when "0010" => txd_s <= din_s(0);
	when "0011" => txd_s <= din_s(1);
	when "0100" => txd_s <= din_s(2);
	when "0101" => txd_s <= din_s(3);
	when "0110" => txd_s <= din_s(4);
	when "0111" => txd_s <= din_s(5);
	when "1000" => txd_s <= din_s(6);
	when "1001" => txd_s <= din_s(7);
	when others => txd_s <= '1';
    end case;
end process;

process(reset,clk)
begin
    if (reset='1') then
	txd <= '1';
    elsif (clk'event and clk='1') then
	if (count_in(4 downto 0)="00001") then
	   txd <= txd_s;
	end if;
    end if;
end process;

end Behavioral;