uart.vhd

256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity uart is
   port  (
	     uartclk      : IN	STD_LOGIC;
	     reset        : IN	STD_LOGIC; 
	     busclk       : IN	STD_LOGIC;
	     din          : IN    STD_LOGIC_VECTOR(7 downto 0);
	     dout         : OUT   STD_LOGIC_VECTOR(7 downto 0);
	     rxd          : IN    STD_LOGIC;
	     txd          : OUT   STD_LOGIC;
	     tfifo_wenb   : IN    STD_LOGIC;
	     rfifo_renb   : IN    STD_LOGIC;
	     full_s       : OUT   STD_LOGIC; --add
         hfull_s      : OUT   STD_LOGIC; --add
         empty_s      : OUT   STD_LOGIC; --add

         --status       : OUT   STD_LOGIC; ----xunb--add--
         full_r       : OUT   STD_LOGIC;
         hfull_r      : OUT   STD_LOGIC;
         empty_r      : OUT   STD_LOGIC);
end uart;   
   
   
architecture arch of uart is
component uart_receive
    port (
    clk      :in std_logic;
	reset    :in std_logic;
	rxd      :in std_logic;
	renb     :out std_logic;
	dout     :out std_logic_vector(7 downto 0));
end component;

component uart_send
    port (
    clk           :in std_logic;
	reset         :in std_logic;
	wenb          :in std_logic;
	din           :in std_logic_vector(7 downto 0);	
	status        :out std_logic;
	txd           :out std_logic);
end component;

component uart_fifo IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrreq		: IN STD_LOGIC ;
		rdreq		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		aclr        : IN STD_LOGIC ;
		q		    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		full		: OUT STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		usedw		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END component;

attribute syn_black_box : boolean;
attribute syn_black_box of uart_fifo: component is true;

signal  data_count_r1:   std_logic_vector(7 downto 0);
signal  rfifo_wenb:   std_logic;
signal  renb      :     std_logic;
signal  renb1     :     std_logic;
signal  renb2     :     std_logic;
signal  renb3     :     std_logic;
signal  dout_uart :	std_logic_vector(7 downto 0);

-----xunb---------
signal  data_count_s1:  std_logic_vector(7 downto 0);
signal  tfifo_renb:     std_logic;
signal  tfifo_renb1:     std_logic;
signal  tfifo_renb2:     std_logic;
signal  wenb      :     std_logic;
signal  wenb1     :     std_logic;
signal  wenb2     :     std_logic;
signal  wenb3     :     std_logic;
signal  din_uart  :	    std_logic_vector(7 downto 0);

signal  data_count_s:   std_logic_vector(7 downto 0);
signal  status_1    :   std_logic;
signal  status_2    :   std_logic; 

signal  tfifo_wenb1:     std_logic;
signal  tfifo_wenb2:     std_logic;
signal  tfifo_wenb3:     std_logic;


-----end--xunb----
begin
----send part---------------------
--uartsend: uart_send
--    port map (
--	clk   => uartclk,
--	reset => reset,
--	wenb   => tfifo_wenb,
--	status  => status,
--	din  => din,
--	txd => txd);

----send part--------------xunb-------
fifo_tr: uart_fifo
   port map (
       clock => busclk,        --must use busclk
       aclr  => reset,
       data  => din,           --form dsp
       wrreq => tfifo_wenb3,   --dsp first wr fifo
       rdreq => tfifo_renb,    --<--
       q     => din_uart,      --to tr uart
       full  => full_s,        --to out
       empty => empty_s,       --to out
       usedw => data_count_s1);--to hfull


--generate tfifo_wenb's logic
process(reset,busclk)
begin
    if(reset='1')then
	   tfifo_wenb1 <= '0';
	   tfifo_wenb2 <= '0';
	   tfifo_wenb3 <= '0';
    elsif(busclk'event and busclk='0')then
         tfifo_wenb1 <= tfifo_wenb;
		 tfifo_wenb2 <= tfifo_wenb1;
		 tfifo_wenb3 <= tfifo_wenb1 and (not tfifo_wenb2); 
    end if;
end process;
----------------------
	  data_count_s <= data_count_s1;

process(reset,busclk,wenb1,status_1)  
begin
    if(reset='1' or wenb1='1')then
       status_2 <= '0';
    elsif(busclk'event and busclk='1')then
	  status_2 <= status_1;
    end if;
end process;


--generate tfifo_renb's logic
process(reset,busclk,data_count_s1,status_2)
begin
    if(reset='1')then
       tfifo_renb1 <= '0';
	   tfifo_renb2 <= '0';
	   tfifo_renb <= '0';
    elsif(busclk'event and busclk='0')then
      if(data_count_s1 >="0001"and status_2='1')then
         tfifo_renb1 <= '1';
		 tfifo_renb2 <= tfifo_renb1;
		 tfifo_renb <= tfifo_renb1 and (not tfifo_renb2);  ---tfifo_renb
    	  else
         tfifo_renb1 <= '0';
		 tfifo_renb2 <= '0';
		 tfifo_renb <= '0';
       end if;
    end if;
end process;


process(reset,tfifo_renb,status_1)
begin
    if(reset='1' or status_1='0')then
           wenb1 <= '0';
    elsif(tfifo_renb'event and tfifo_renb='0')then
           wenb1 <= '1';
    end if;
end process;

--generate wenb's logic
process(reset,uartclk)
begin
    if(reset='1')then
        wenb <= '0';
	    wenb2 <= '0';
	    wenb3 <= '0';
    elsif(uartclk'event and uartclk='1')then
        wenb2 <= wenb1;
		wenb3 <= wenb2;
	    wenb <= wenb2 and (not wenb3) ;      --wenb
    end if;
end process;        

--half-full flag
process(reset,data_count_s1)                 ---half-full
begin
    if(reset='1')then
       hfull_s <= '0';
    elsif(data_count_s1 >="01111111" )then
       hfull_s <= '1';
    else
       hfull_s <= '0';
    end if;
end process;       
----
uartsend: uart_send
    port map (
	clk   => uartclk,
	reset => reset,
	wenb   => wenb,
	status  => status_1, 
	din  => din_uart,
	txd => txd);
	
-----end xunb-------

-----receive part------------------
uartreceive: uart_receive
    port map (
	clk   => uartclk,
	reset => reset,
	rxd   => rxd,
	renb  => renb,
	dout  => dout_uart);

process(reset,busclk)
begin
    if(reset='1')then
       renb1 <= '0';
	   renb2 <= '0';
	   renb3 <= '0';
    elsif(busclk'event and busclk='0' )then
       renb1 <= renb;
	   renb2 <= renb1;
	   renb3 <= renb1 and (not renb2);
    end if;
end process;      

fifo_re: uart_fifo
   port map (
       clock => busclk,
       aclr => reset,
       data => dout_uart,
       wrreq => renb3,
       rdreq => rfifo_renb,
       q => dout,
       full => full_r,
       empty => empty_r,
       usedw => data_count_r1);

--half-full flag
process(reset,data_count_r1)
begin
    if(reset='1')then
       hfull_r <= '0';
    elsif(data_count_r1 > "00000000" )then
       hfull_r <= '1';
    else
	   hfull_r <= '0';
    end if;
end process;      

end arch;