uart_receive.vhd

256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity uart_receive is
  port(clk      :in std_logic;
       reset    :in std_logic;
       rxd      :in std_logic;
       renb     :out std_logic;
       dout     :out std_logic_vector(7 downto 0));
end uart_receive;

architecture rtl of uart_receive is
   
signal dout_s:std_logic_vector(7 downto 0);
signal count:std_logic_vector(8 downto 0);
signal rxdf:std_logic;
signal rxdsa:std_logic_vector(2 downto 0);
signal rxdaa:std_logic;

begin
process(count(4 downto 0),rxd,rxdsa)
begin
    CASE count(4 downto 0) IS
	    WHEN "01000" =>
		    rxdsa(0)<=rxd;
	    WHEN "01010" =>
            rxdsa(1)<=rxd;
	    WHEN "01100" =>
            rxdsa(2)<=rxd;
	    WHEN OTHERS =>
		    rxdsa<=rxdsa;
     END CASE;
end process;

PROCESS(rxdsa)
begin
    case rxdsa is
        when"000"=>rxdaa<='0';
        when"001"=>rxdaa<='0';
        when"010"=>rxdaa<='0';
        when"011"=>rxdaa<='1';
        when"100"=>rxdaa<='0';
        when"101"=>rxdaa<='1';
        when"110"=>rxdaa<='1';
        when others=>rxdaa<='1';
    end case;	     
end process;
  
process(clk,reset)
variable counti:integer range 0 to 450;
begin
    if(reset='1')then
	rxdf<='0';
	renb<='0';
	counti:=0;
    elsif(clk'event and clk='1') then      
        if(rxd='0' and rxdf='0')then
	   rxdf<='1';
           renb<='0'; 
           counti:=128;
        elsif(rxdf='1'and (counti>=128) and (counti<447))then
           if(count(8 downto 5)="0100"and count(4 downto 0)="10010"and rxdaa='1')then
	      rxdf<='0';
	      renb<='0';
	      counti:=0;          
           end if; 
           if(counti=436 and rxdaa='1')then 
              renb<='1';
	      rxdf<='0';
	      counti:=0; 
           end if;
 	   if (count(4 downto 0)="11000") then
              counti:=counti+8;
           else 
              counti:=counti+1;
	   end if;
	else
           rxdf<='0';
	   renb<='0';
           counti:=0;
        end if;
	count<=conv_std_logic_vector(counti,9);
    end if;
end process;

process(clk)
begin
    if(clk'event and clk='1')then
        if((count(8 downto 5)<"1101")and (count(4 downto 0)="10100"))then
           dout_s(7)<=rxdaa;
           for i in 0 to 6 loop
              dout_s(i)<=dout_s(i+1);
           end loop;
        elsif((count(8 downto 5)="1101")and (count(4 downto 0)="10010"))then 
           if (rxdaa='1')then
              dout<=dout_s;
           end if;
        end if;
    end if;
end process;

end rtl;