shuju_map.v

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: H.42
//  \   \         Application: netgen
//  /   /         Filename: shuju_map.v
// /___/   /\     Timestamp: Mon Jan 14 14:19:23 2008
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -s 4 -pcf shuju.pcf -sdf_anno true -w -ofmt verilog -sim shuju_map.ncd shuju_map.v 
// Device	: 3s400pq208-4 (PRODUCTION 1.37 2005-07-22)
// Input file	: shuju_map.ncd
// Output file	: shuju_map.v
// # of Modules	: 1
// Design Name	: shuju
// Xilinx	: D:/Xilinx
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Verification Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module shuju (
  sclk, sdata, datain
);
  input sclk;
  output sdata;
  output [15 : 0] datain;
  wire GLOBAL_LOGIC0;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \datain<4>/ENABLE ;
  wire \datain<4>/O ;
  wire \datain<5>/ENABLE ;
  wire \datain<5>/O ;
  wire \datain<6>/ENABLE ;
  wire \datain<6>/O ;
  wire \datain<7>/ENABLE ;
  wire \datain<7>/O ;
  wire \datain<8>/ENABLE ;
  wire \datain<8>/O ;
  wire \datain<9>/ENABLE ;
  wire \datain<9>/O ;
  wire \datain<10>/ENABLE ;
  wire \datain<10>/O ;
  wire \datain<11>/ENABLE ;
  wire \datain<11>/O ;
  wire \sdata/ENABLE ;
  wire \sdata/O ;
  wire \datain<12>/ENABLE ;
  wire \datain<12>/O ;
  wire \datain<13>/ENABLE ;
  wire \datain<13>/O ;
  wire \datain<14>/ENABLE ;
  wire \datain<14>/O ;
  wire \datain<15>/ENABLE ;
  wire \datain<15>/O ;
  wire \datain<0>/ENABLE ;
  wire \datain<0>/O ;
  wire \datain<1>/ENABLE ;
  wire \datain<1>/O ;
  wire \datain<2>/ENABLE ;
  wire \datain<2>/O ;
  wire \datain<3>/ENABLE ;
  wire \datain<3>/O ;
  initial $sdf_annotate("shuju_map.sdf");
  X_OPAD \datain<4>/PAD  (
    .PAD(datain[4])
  );
  X_TRI datain_4_OBUF (
    .I(\datain<4>/O ),
    .CTL(\datain<4>/ENABLE ),
    .O(datain[4])
  );
  X_INV \datain<4>/ENABLEINV  (
    .I(GTS),
    .O(\datain<4>/ENABLE )
  );
  X_OPAD \datain<5>/PAD  (
    .PAD(datain[5])
  );
  X_TRI datain_5_OBUF (
    .I(\datain<5>/O ),
    .CTL(\datain<5>/ENABLE ),
    .O(datain[5])
  );
  X_INV \datain<5>/ENABLEINV  (
    .I(GTS),
    .O(\datain<5>/ENABLE )
  );
  X_OPAD \datain<6>/PAD  (
    .PAD(datain[6])
  );
  X_TRI datain_6_OBUF (
    .I(\datain<6>/O ),
    .CTL(\datain<6>/ENABLE ),
    .O(datain[6])
  );
  X_INV \datain<6>/ENABLEINV  (
    .I(GTS),
    .O(\datain<6>/ENABLE )
  );
  X_OPAD \datain<7>/PAD  (
    .PAD(datain[7])
  );
  X_TRI datain_7_OBUF (
    .I(\datain<7>/O ),
    .CTL(\datain<7>/ENABLE ),
    .O(datain[7])
  );
  X_INV \datain<7>/ENABLEINV  (
    .I(GTS),
    .O(\datain<7>/ENABLE )
  );
  X_OPAD \datain<8>/PAD  (
    .PAD(datain[8])
  );
  X_TRI datain_8_OBUF (
    .I(\datain<8>/O ),
    .CTL(\datain<8>/ENABLE ),
    .O(datain[8])
  );
  X_INV \datain<8>/ENABLEINV  (
    .I(GTS),
    .O(\datain<8>/ENABLE )
  );
  X_OPAD \datain<9>/PAD  (
    .PAD(datain[9])
  );
  X_TRI datain_9_OBUF (
    .I(\datain<9>/O ),
    .CTL(\datain<9>/ENABLE ),
    .O(datain[9])
  );
  X_INV \datain<9>/ENABLEINV  (
    .I(GTS),
    .O(\datain<9>/ENABLE )
  );
  X_OPAD \datain<10>/PAD  (
    .PAD(datain[10])
  );
  X_TRI datain_10_OBUF (
    .I(\datain<10>/O ),
    .CTL(\datain<10>/ENABLE ),
    .O(datain[10])
  );
  X_INV \datain<10>/ENABLEINV  (
    .I(GTS),
    .O(\datain<10>/ENABLE )
  );
  X_OPAD \datain<11>/PAD  (
    .PAD(datain[11])
  );
  X_TRI datain_11_OBUF (
    .I(\datain<11>/O ),
    .CTL(\datain<11>/ENABLE ),
    .O(datain[11])
  );
  X_INV \datain<11>/ENABLEINV  (
    .I(GTS),
    .O(\datain<11>/ENABLE )
  );
  X_OPAD \sdata/PAD  (
    .PAD(sdata)
  );
  X_TRI sdata_OBUF (
    .I(\sdata/O ),
    .CTL(\sdata/ENABLE ),
    .O(sdata)
  );
  X_INV \sdata/ENABLEINV  (
    .I(GTS),
    .O(\sdata/ENABLE )
  );
  X_OPAD \datain<12>/PAD  (
    .PAD(datain[12])
  );
  X_TRI datain_12_OBUF (
    .I(\datain<12>/O ),
    .CTL(\datain<12>/ENABLE ),
    .O(datain[12])
  );
  X_INV \datain<12>/ENABLEINV  (
    .I(GTS),
    .O(\datain<12>/ENABLE )
  );
  X_OPAD \datain<13>/PAD  (
    .PAD(datain[13])
  );
  X_TRI datain_13_OBUF (
    .I(\datain<13>/O ),
    .CTL(\datain<13>/ENABLE ),
    .O(datain[13])
  );
  X_INV \datain<13>/ENABLEINV  (
    .I(GTS),
    .O(\datain<13>/ENABLE )
  );
  X_OPAD \datain<14>/PAD  (
    .PAD(datain[14])
  );
  X_TRI datain_14_OBUF (
    .I(\datain<14>/O ),
    .CTL(\datain<14>/ENABLE ),
    .O(datain[14])
  );
  X_INV \datain<14>/ENABLEINV  (
    .I(GTS),
    .O(\datain<14>/ENABLE )
  );
  X_OPAD \datain<15>/PAD  (
    .PAD(datain[15])
  );
  X_TRI datain_15_OBUF (
    .I(\datain<15>/O ),
    .CTL(\datain<15>/ENABLE ),
    .O(datain[15])
  );
  X_INV \datain<15>/ENABLEINV  (
    .I(GTS),
    .O(\datain<15>/ENABLE )
  );
  X_OPAD \datain<0>/PAD  (
    .PAD(datain[0])
  );
  X_TRI datain_0_OBUF (
    .I(\datain<0>/O ),
    .CTL(\datain<0>/ENABLE ),
    .O(datain[0])
  );
  X_INV \datain<0>/ENABLEINV  (
    .I(GTS),
    .O(\datain<0>/ENABLE )
  );
  X_OPAD \datain<1>/PAD  (
    .PAD(datain[1])
  );
  X_TRI datain_1_OBUF (
    .I(\datain<1>/O ),
    .CTL(\datain<1>/ENABLE ),
    .O(datain[1])
  );
  X_INV \datain<1>/ENABLEINV  (
    .I(GTS),
    .O(\datain<1>/ENABLE )
  );
  X_OPAD \datain<2>/PAD  (
    .PAD(datain[2])
  );
  X_TRI datain_2_OBUF (
    .I(\datain<2>/O ),
    .CTL(\datain<2>/ENABLE ),
    .O(datain[2])
  );
  X_INV \datain<2>/ENABLEINV  (
    .I(GTS),
    .O(\datain<2>/ENABLE )
  );
  X_OPAD \datain<3>/PAD  (
    .PAD(datain[3])
  );
  X_TRI datain_3_OBUF (
    .I(\datain<3>/O ),
    .CTL(\datain<3>/ENABLE ),
    .O(datain[3])
  );
  X_INV \datain<3>/ENABLEINV  (
    .I(GTS),
    .O(\datain<3>/ENABLE )
  );
  X_ZERO GLOBAL_LOGIC0_GND (
    .O(GLOBAL_LOGIC0)
  );
  X_BUF \datain<4>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<4>/O )
  );
  X_BUF \datain<5>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<5>/O )
  );
  X_BUF \datain<6>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<6>/O )
  );
  X_BUF \datain<7>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<7>/O )
  );
  X_BUF \datain<8>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<8>/O )
  );
  X_BUF \datain<9>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<9>/O )
  );
  X_BUF \datain<10>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<10>/O )
  );
  X_BUF \datain<11>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<11>/O )
  );
  X_BUF \sdata/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\sdata/O )
  );
  X_BUF \datain<12>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<12>/O )
  );
  X_BUF \datain<13>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<13>/O )
  );
  X_BUF \datain<14>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<14>/O )
  );
  X_BUF \datain<15>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<15>/O )
  );
  X_BUF \datain<0>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<0>/O )
  );
  X_BUF \datain<1>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<1>/O )
  );
  X_BUF \datain<2>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<2>/O )
  );
  X_BUF \datain<3>/OUTPUT/OFF/OMUX  (
    .I(GLOBAL_LOGIC0),
    .O(\datain<3>/O )
  );
endmodule