icx229.syr

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

 001   | 01
 010   | 10
-------------------
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <FSM_3> on signal <state2[1:4]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 000   | 1000
 001   | 0100
 010   | 0010
 011   | 0001
-------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <FSM_2> on signal <state1[1:3]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 011   | 011
 100   | 100
 101   | 101
 110   | 110
 111   | 111
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <state0[1:4]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 000   | 1000
 001   | 0100
 010   | 0010
 011   | 0001
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 000   | 00
 001   | 01
 010   | 10
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 16
# Adders/Subtractors               : 14
 15-bit adder                      : 10
 3-bit adder                       : 1
 31-bit adder                      : 3
# Registers                        : 82
 1-bit register                    : 68
 15-bit register                   : 10
 3-bit register                    : 1
 31-bit register                   : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ICX229> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ICX229, actual ratio is 16.
FlipFlop state13_FFd1 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ICX229.ngr
Top Level Output File Name         : ICX229
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 12

Macro Statistics :
# Registers                        : 24
#      1-bit register              : 10
#      15-bit register             : 10
#      3-bit register              : 1
#      31-bit register             : 3
# Adders/Subtractors               : 13
#      15-bit adder                : 10
#      31-bit adder                : 3

Cell Usage :
# BELS                             : 1589
#      GND                         : 1
#      INV                         : 15
#      LUT1                        : 229
#      LUT1_L                      : 1
#      LUT2                        : 87
#      LUT2_D                      : 11
#      LUT2_L                      : 13
#      LUT3                        : 55
#      LUT3_D                      : 12
#      LUT3_L                      : 36
#      LUT4                        : 261
#      LUT4_D                      : 78
#      LUT4_L                      : 317
#      MUXCY                       : 230
#      MUXF5                       : 12
#      VCC                         : 1
#      XORCY                       : 230
# FlipFlops/Latches                : 315
#      FDR                         : 245
#      FDRE                        : 24
#      FDRS                        : 33
#      FDS                         : 11
#      FDSE                        : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 1
#      OBUF                        : 10
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     597  out of   3584    16%  
 Number of Slice Flip Flops:           315  out of   7168     4%  
 Number of 4 input LUTs:              1100  out of   7168    15%  
 Number of bonded IOBs:                 12  out of    141     8%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 315   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 12.963ns (Maximum Frequency: 77.143MHz)
   Minimum input arrival time before clock: 6.673ns
   Maximum output required time after clock: 7.271ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 12.963ns (frequency: 77.143MHz)
  Total number of paths / destination ports: 46403 / 374
-------------------------------------------------------------------------
Delay:               12.963ns (Levels of Logic = 7)
  Source:            b_11 (FF)
  Destination:       a_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: b_11 to a_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              4   0.720   1.256  b_11 (b_11)
     LUT2:I0->O            1   0.551   0.869  Ker2047 (CHOICE943)
     LUT4:I2->O            7   0.551   1.134  Ker20429 (N204)
     LUT3:I2->O            7   0.551   1.134  Ker2321 (N232)
     LUT4:I2->O            1   0.551   0.827  Ker9443 (CHOICE828)
     LUT4_D:I3->LO         1   0.551   0.126  Ker9452 (N3860)
     LUT4:I3->O           14   0.551   1.213  Ker491 (N49)
     LUT4:I3->O            1   0.551   0.801  _n0134<0>60 (CHOICE1111)
     FDRS:S                    1.026          a_0
    ----------------------------------------
    Total                     12.963ns (5.603ns logic, 7.360ns route)
                                       (43.2% logic, 56.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 315 / 315
-------------------------------------------------------------------------
Offset:              6.673ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       o_3 (FF)
  Destination Clock: clk rising

  Data Path: rst to o_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.821   0.801  rst_IBUF (rst_IBUF)
     INV:I->O            315   0.551   3.474  state_FFd2_N01_INV_0 (state_FFd2_N0)
     FDRS:R                    1.026          state_FFd2
    ----------------------------------------
    Total                      6.673ns (2.398ns logic, 4.275ns route)
                                       (35.9% logic, 64.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 10 / 10
-------------------------------------------------------------------------
Offset:              7.271ns (Levels of Logic = 1)
  Source:            h1 (FF)
  Destination:       h1 (PAD)
  Source Clock:      clk rising

  Data Path: h1 to h1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q             3   0.720   0.907  h1 (h1_OBUF)
     OBUF:I->O                 5.644          h1_OBUF (h1)
    ----------------------------------------
    Total                      7.271ns (6.364ns logic, 0.907ns route)
                                       (87.5% logic, 12.5% route)

=========================================================================
CPU : 37.77 / 40.77 s | Elapsed : 38.00 / 40.00 s
 
--> 

Total memory usage is 109400 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)