top.v

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 7.1.04i
//  \   \         Application : sch2verilog
//  /   /         Filename : top.vf
// /___/   /\     Timestamp : 01/14/2008 15:05:54
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: D:/Xilinx/bin/nt/sch2verilog.exe -intstyle ise -family spartan3 -w top.sch top.vf
//Design Name: top
//Device: spartan3
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be 
//    synthesized and simulated, but it should not be modified. 
//
`timescale 1ns / 1ps

module top(clk, 
           rst, 
           adcck, 
           clkbp, 
           clpdm, 
           clpob, 
           h1, 
           h2, 
           pblk, 
           r, 
           reset, 
           sclk, 
           shd, 
           shp, 
           sload, 
           sub, 
           v1, 
           v1h, 
           v2, 
           v3, 
           v3h, 
           v4);

    input clk;
    input rst;
   output adcck;
   output clkbp;
   output clpdm;
   output clpob;
   output h1;
   output h2;
   output pblk;
   output r;
   output reset;
   output sclk;
   output shd;
   output shp;
   output sload;
   output sub;
   output v1;
   output v1h;
   output v2;
   output v3;
   output v3h;
   output v4;
   
   wire sdata;
   wire XLXN_10;
   
   ICX229 XLXI_1 (.clk(clkbp), 
                  .rst(rst), 
                  .h1(h1), 
                  .h2(h2), 
                  .r(r), 
                  .sub(sub), 
                  .v1(v1), 
                  .v1h(v1h), 
                  .v2(v2), 
                  .v3(v3), 
                  .v3h(v3h), 
                  .v4(v4));
   serial XLXI_2 (.clk(XLXN_10), 
                  .rst(rst), 
                  .reset(reset), 
                  .sclk(sclk), 
                  .sload(sload));
   VSP2232 XLXI_3 (.clk(clkbp), 
                   .rst(rst), 
                   .adcck(adcck), 
                   .clpdm(clpdm), 
                   .clpob(clpob), 
                   .pblk(pblk), 
                   .shd(shd), 
                   .shp(shp));
   shuju XLXI_7 (.sclk(), 
                 .sdata(sdata));
   clk4 XLXI_8 (.CLKIN_IN(clk), 
                .CLKIN_IBUFG_OUT(), 
                .CLK0_OUT(XLXN_10), 
                .CLK2X_OUT(clkbp), 
                .LOCKED_OUT());
endmodule