serial.syr

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

 0001  | 1
-------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <FSM_2> on signal <s3[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <s2[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <s1[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 5
# Adders/Subtractors               : 2
 8-bit adder                       : 2
# Counters                         : 2
 8-bit up counter                  : 2
# Registers                        : 10
 1-bit register                    : 8
 8-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <serial> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block serial, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : serial.ngr
Top Level Output File Name         : serial
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 5

Macro Statistics :
# Registers                        : 7
#      1-bit register              : 3
#      8-bit register              : 4
# Adders/Subtractors               : 4
#      8-bit adder                 : 4

Cell Usage :
# BELS                             : 152
#      GND                         : 1
#      INV                         : 5
#      LUT1                        : 14
#      LUT1_L                      : 14
#      LUT2                        : 7
#      LUT2_L                      : 2
#      LUT3                        : 1
#      LUT3_D                      : 2
#      LUT3_L                      : 10
#      LUT4                        : 16
#      LUT4_D                      : 5
#      LUT4_L                      : 17
#      MUXCY                       : 28
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 28
# FlipFlops/Latches                : 40
#      FDR                         : 15
#      FDRE                        : 19
#      FDRS                        : 3
#      FDRSE                       : 1
#      FDS                         : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 4
#      IBUF                        : 1
#      OBUF                        : 3
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      57  out of   3584     1%  
 Number of Slice Flip Flops:            40  out of   7168     0%  
 Number of 4 input LUTs:                88  out of   7168     1%  
 Number of bonded IOBs:                  5  out of    141     3%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 40    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.468ns (Maximum Frequency: 133.905MHz)
   Minimum input arrival time before clock: 5.098ns
   Maximum output required time after clock: 7.271ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 7.468ns (frequency: 133.905MHz)
  Total number of paths / destination ports: 931 / 62
-------------------------------------------------------------------------
Delay:               7.468ns (Levels of Logic = 4)
  Source:            sc_2 (FF)
  Destination:       sb_2 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: sc_2 to sb_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.720   1.246  sc_2 (sc_2)
     LUT2:I0->O            1   0.551   0.869  _n00086 (CHOICE17)
     LUT4:I2->O            7   0.551   1.092  _n000828 (_n0008)
     LUT4:I3->O            7   0.551   1.134  Ker41 (N4)
     LUT4_L:I2->LO         1   0.551   0.000  _n0021<5>1 (_n0021<5>)
     FDR:D                     0.203          sb_5
    ----------------------------------------
    Total                      7.468ns (3.127ns logic, 4.341ns route)
                                       (41.9% logic, 58.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 40 / 40
-------------------------------------------------------------------------
Offset:              5.098ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       sb_2 (FF)
  Destination Clock: clk rising

  Data Path: rst to sb_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.821   0.801  rst_IBUF (rst_IBUF)
     INV:I->O             40   0.551   1.899  s1_FFd1_N01_INV_0 (s1_FFd1_N0)
     FDRS:R                    1.026          s1_FFd1
    ----------------------------------------
    Total                      5.098ns (2.398ns logic, 2.700ns route)
                                       (47.0% logic, 53.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              7.271ns (Levels of Logic = 1)
  Source:            sclk (FF)
  Destination:       sclk (PAD)
  Source Clock:      clk rising

  Data Path: sclk to sclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              3   0.720   0.907  sclk (sclk_OBUF)
     OBUF:I->O                 5.644          sclk_OBUF (sclk)
    ----------------------------------------
    Total                      7.271ns (6.364ns logic, 0.907ns route)
                                       (87.5% logic, 12.5% route)

=========================================================================
CPU : 8.59 / 10.34 s | Elapsed : 9.00 / 10.00 s
 
--> 

Total memory usage is 101656 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)