__projnav.log

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "top_map.mrp" for details.




Started process "Place & Route".




Constraints file: top.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "top" is an NCD, version 3.1, device xc3s400, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.37 2005-07-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            23 out of 141    16%
      Number of LOCed IOBs             0 out of 23      0%

   Number of Slices                  724 out of 3584   20%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98a726) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.8
......................................................................................
Phase 6.8 (Checksum:a0b549) REAL time: 3 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 4 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 4 secs 

Writing design to file top.ncd


Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 3 secs 

Starting Router

Phase 1: 4921 unrouted;       REAL time: 4 secs 

Phase 2: 4620 unrouted;       REAL time: 5 secs 

Phase 3: 1918 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 6 secs 

WARNING:Route - CLK Net:clkbp_OBUF
may have excessive skew because 1 NON-CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 5 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|          clkbp_OBUF |      BUFGMUX7| No   |  249 |  0.060     |  1.074      |
+---------------------+--------------+------+------+------------+-------------+
|             XLXN_10 |      BUFGMUX6| No   |   26 |  0.060     |  1.074      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  90 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 1
Number of info messages: 1

Writing design to file top.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "top" is an NCD, version 3.1, device xc3s400, package pq208, speed -4

Analysis completed Mon Jan 14 13:13:20 2008
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 4 secs 




Started process "Generate Post-Place & Route Simulation Model".

INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM simulation library for
   correct compilation and simulation. 
INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
   Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
   simulator compile and invocation commands in order to allow proper
   initialization of the design. If simulation is performed within Project
   Navigator, this will be taken care of automatically. For more information on
   compiling and performing Xilinx simulation, consult the online Synthesis and
   Verification Design Guide:
   http://support.xilinx.com/support/software_manuals.htm 





Project Navigator Auto-Make Log File
-------------------------------------





Project Navigator Auto-Make Log File
-------------------------------------





Project Navigator Auto-Make Log File
-------------------------------------





Project Navigator Auto-Make Log File
-------------------------------------




Started process "Create Schematic Symbol".

xaw2spl: Completed successfully





Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Source".

xaw2verilog: Completed successfully










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "ICX229.v"
Module <ICX229> compiled
Compiling verilog file "serial.v"
Module <serial> compiled
Compiling verilog file "VSP2232.v"
Module <VSP2232> compiled
Compiling verilog file "clk4.v"
Module <clk4> compiled
Compiling verilog file "shuju.v"
Module <shuju> compiled
Compiling verilog file "top.vf"
Module <top> compiled
No errors in compilation
Analysis of file <"top.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <top>.
Module <top> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <top>.
Analyzing module <ICX229>.
Module <ICX229> is correct for synthesis.
 
Analyzing module <serial>.
Module <serial> is correct for synthesis.
 
Analyzing module <VSP2232>.
Module <VSP2232> is correct for synthesis.
 
Analyzing module <clk4>.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "clk4.v" line 52: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribut