__projnav.log

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

 000   | 1000
 001   | 0100
 010   | 0010
 011   | 0001
-------------------
Analyzing FSM <FSM_12> for best encoding.
Optimizing FSM <FSM_12> on signal <state1[1:3]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 011   | 011
 100   | 100
 101   | 101
 110   | 110
 111   | 111
-------------------
Analyzing FSM <FSM_11> for best encoding.
Optimizing FSM <FSM_11> on signal <state0[1:4]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 000   | 1000
 001   | 0100
 010   | 0010
 011   | 0001
-------------------
Analyzing FSM <FSM_10> for best encoding.
Optimizing FSM <FSM_10> on signal <state[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 000   | 00
 001   | 01
 010   | 10
-------------------
Analyzing FSM <FSM_9> for best encoding.
Optimizing FSM <FSM_9> on signal <s5[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Analyzing FSM <FSM_8> for best encoding.
Optimizing FSM <FSM_8> on signal <s4[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Analyzing FSM <FSM_7> for best encoding.
Optimizing FSM <FSM_7> on signal <s3[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Analyzing FSM <FSM_6> for best encoding.
Optimizing FSM <FSM_6> on signal <s2[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Analyzing FSM <FSM_5> for best encoding.
Optimizing FSM <FSM_5> on signal <s1[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Analyzing FSM <FSM_4> for best encoding.
Optimizing FSM <FSM_4> on signal <t5[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 0000  | 00
 0001  | 01
 0010  | 10
-------------------
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <FSM_3> on signal <t4[1:5]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 0000  | 10000
 0001  | 01000
 0010  | 00100
 0011  | 00010
 0100  | 00001
-------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <FSM_2> on signal <t3[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 00
 0001  | 01
 0010  | 11
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <t2[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <t1[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0
 0001  | 1
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 26
# Adders/Subtractors               : 22
 15-bit adder                      : 12
 3-bit adder                       : 1
 31-bit adder                      : 3
 4-bit adder                       : 3
 5-bit adder                       : 1
 8-bit adder                       : 2
# Counters                         : 2
 8-bit up counter                  : 2
# Registers                        : 118
 1-bit register                    : 94
 15-bit register                   : 12
 16-bit register                   : 1
 3-bit register                    : 2
 31-bit register                   : 3
 4-bit register                    : 3
 5-bit register                    : 1
 8-bit register                    : 2
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <data_0> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_1> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_2> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <zhuangtai_0> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1710 - FF/Latch  <data_13> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_12> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_15> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sdata> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_14> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <zhuangtai_1> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_3> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_4> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_5> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_6> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_7> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_8> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_9> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_10> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_11> (without init value) has a constant value of 0 in block <shuju>.
WARNING:Xst:1291 - FF/Latch <count_4> is unconnected in block <shuju>.
WARNING:Xst:1291 - FF/Latch <count_3> is unconnected in block <shuju>.
WARNING:Xst:1291 - FF/Latch <zhuangtai_2> is unconnected in block <shuju>.
WARNING:Xst:1291 - FF/Latch <count_0> is unconnected in block <shuju>.
WARNING:Xst:1291 - FF/Latch <count_2> is unconnected in block <shuju>.
WARNING:Xst:1291 - FF/Latch <count_1> is unconnected in block <shuju>.

Optimizing unit <top> ...

Optimizing unit <VSP2232> ...

Optimizing unit <ICX229> ...

Optimizing unit <serial> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 19.
FlipFlop XLXI_1/state13_FFd1 has been replicated 1 time(s)
FlipFlop XLXI_1/state13_FFd2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     730  out of   3584    20%  
 Number of Slice Flip Flops:           415  out of   7168     5%  
 Number of 4 input LUTs:              1331  out of   7168    18%  
 Number of bonded IOBs:                 23  out of    141    16%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | XLXI_6/DCM_INST:CLKFX  | 375   |
clk                                | XLXI_6/DCM_INST:CLK0   | 40    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 47.768ns (Maximum Frequency: 20.935MHz)
   Minimum input arrival time before clock: 7.316ns
   Maximum output required time after clock: 7.271ns
   Maximum combinational path delay: No path found

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\test\icx229al/_ngo -nt timestamp -i
-p xc3s400-pq208-4 top.ngc top.ngd 

Reading NGO file 'D:/test/ICX229AL/top.ngc' ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s400pq208-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         411 out of   7,168    5%
  Number of 4 input LUTs:           1,065 out of   7,168   14%
Logic Distribution:
  Number of occupied Slices:                          724 out of   3,584   20%
    Number of Slices containing only related logic:     724 out of     724  100%
    Number of Slices containing unrelated logic:          0 out of     724    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,351 out of   7,168   18%
  Number used as logic:              1,065
  Number used as a route-thru:         286
  Number of bonded IOBs:               23 out of     141   16%
    IOB Flip Flops:                     4
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  18,495
Additional JTAG gate count for IOBs:  1,104
Peak Memory Usage:  120 MB