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SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

    Summary:
	inferred  25 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <shuju> synthesized.


Synthesizing Unit <clk4>.
    Related source file is "clk4.v".
Unit <clk4> synthesized.


Synthesizing Unit <VSP2232>.
    Related source file is "VSP2232.v".
    Found finite state machine <FSM_0> for signal <t1>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 3                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <t2>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 3                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <t3>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 1                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_3> for signal <t4>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 10                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_4> for signal <t5>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <shp>.
    Found 1-bit register for signal <adcck>.
    Found 1-bit register for signal <clpdm>.
    Found 1-bit register for signal <pblk>.
    Found 1-bit register for signal <clpob>.
    Found 1-bit register for signal <shd>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0033> created at line 83.
    Found 4-bit adder for signal <$n0038> created at line 23.
    Found 4-bit adder for signal <$n0039> created at line 53.
    Found 15-bit adder for signal <$n0041> created at line 118.
    Found 15-bit adder for signal <$n0042> created at line 169.
    Found 4-bit adder for signal <$n0043>.
    Found 4-bit register for signal <va>.
    Found 4-bit register for signal <vb>.
    Found 4-bit register for signal <vc>.
    Found 15-bit register for signal <vd>.
    Found 15-bit register for signal <ve>.
    Summary:
	inferred   5 Finite State Machine(s).
	inferred  48 D-type flip-flop(s).
	inferred   5 Adder/Subtractor(s).
	inferred   4 Multiplexer(s).
Unit <VSP2232> synthesized.


Synthesizing Unit <serial>.
    Related source file is "serial.v".
    Found finite state machine <FSM_5> for signal <s1>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 3                                              |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_6> for signal <s2>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 4                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0003 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_7> for signal <s3>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 3                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_8> for signal <s4>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 3                                              |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0011 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_9> for signal <s5>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 4                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <reset>.
    Found 1-bit register for signal <sload>.
    Found 1-bit register for signal <sclk>.
    Found 8-bit adder for signal <$n0025> created at line 41.
    Found 8-bit adder for signal <$n0026> created at line 97.
    Found 8-bit up counter for signal <sa>.
    Found 8-bit register for signal <sb>.
    Found 8-bit up counter for signal <sc>.
    Found 8-bit register for signal <sd>.
    Summary:
	inferred   5 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  19 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <serial> synthesized.


Synthesizing Unit <ICX229>.
    Related source file is "ICX229.v".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state1> of Case statement line 108 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'init' attribute on signal <state1> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found finite state machine <FSM_10> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 8                                              |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_11> for signal <state0>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 4                                              |
    | Inputs             | 0                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0008 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_12> for signal <state1>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 8                                              |
    | Inputs             | 0                                              |
    | Outputs            | 10                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0012 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_13> for signal <state2>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 4                                              |
    | Inputs             | 0                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0021 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_14> for signal <state3>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_15> for signal <state4>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 58                                             |
    | Inputs             | 16                                             |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_16> for signal <state5>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 12                                             |
    | Inputs             | 8                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_17> for signal <state7>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 37                                             |
    | Inputs             | 11                                             |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |