serial_timesim.nlf

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

Release 7.1.04i - netgen H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -s 4 -pcf serial.pcf -sdf_anno true -w -ofmt
verilog -sim serial.ncd serial_timesim.v  

Read and Annotate design 'serial.ncd' ...
Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "serial" is an NCD, version 3.1, device xc3s400, package pq208, speed -4
Loading constraints from 'serial.pcf'...
The speed grade (-4) differs from the speed grade specified in the .ncd file
(-4).
The number of routable networks is 110
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog SDF file 'serial_timesim.sdf' ...
Writing Verilog netlist file 'serial_timesim.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM simulation library for
   correct compilation and simulation. 
INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
   Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
   simulator compile and invocation commands in order to allow proper
   initialization of the design. If simulation is performed within Project
   Navigator, this will be taken care of automatically. For more information on
   compiling and performing Xilinx simulation, consult the online Synthesis and
   Verification Design Guide:
   http://support.xilinx.com/support/software_manuals.htm 
Number of warnings: 0
Number of info messages: 2
Total memory usage is 72904 kilobytes